Circuit and method for contact pad isolation

Abstract

A circuit is provided to isolate a contact pad from a logic circuit of a die once the contact pad is no longer needed. This circuit can take many forms including a CMOS multiplexer controlled by a fuse or anti-fuse, an NMOS or PMOS pass gate controlled by a fuse or anti-fuse, or even a fusible link which is severed to effect isolation. Additionally, a circuit is provided that switchably isolates one of two contact pads from a logic circuit.

1 . A signal regulation device coupled between a first conductive path and a second conductive path, comprising: 
 a signal reception device configured to carry a first signal having a first voltage and a second signal having a second voltage;    a signal control device coupled to said signal reception device and having an initial mode and an isolation mode, wherein: 
 said signal control device is configured to accept said first signal and divert said second signal during said initial mode, and  
 said signal control device is further configured to accept said second signal and divert said first signal during said isolation mode; and  
   a signal transmission device coupled to said first conductive path, said second conductive path, and to said signal control device, wherein: 
 said communication device is configured to receive a diverted signal selectively comprising said first signal and said second signal, and  
 said communication device is configured to allow electrical communication between said first conductive path and said second conductive path in response to receiving said first signal, and said communication device is further configured to prevent said electrical communication in response to receiving said second signal.  
   
   
   
       2 . The signal regulation device in  claim 1 , wherein said first voltage is higher than said second voltage.  
   
   
       3 . The signal regulation device in  claim 1 , wherein said second voltage is higher than said first voltage.  
   
   
       4 . A test mode completion device for a circuit coupled to a redundant contact pad through a test conduit, comprising: 
 an isolation element, wherein: 
 said isolation element is incorporated within said test conduit; and  
 said isolation element is configured to electrically sever said test conduit before said circuit enters a non-test mode.  
   
   
   
       5 . The test mode completion device in  claim 4 , wherein said isolation element is configured to physically sever said test conduit before said logic circuit enters a non-test mode.  
   
   
       6 . The test mode completion device in  claim 5 , wherein said isolation element comprises a fuse.  
   
   
       7 . A test device for an integrated device having a no-connect pin and a die, wherein said die has a logic circuit as well as a test contact pad coupled to said no-connect pin, comprising: 
 an isolation circuit coupled to said test contact pad and to said logic circuit, wherein said isolation circuit is configured to establish electrical communication between said test contact pad and to said logic circuit in a primary mode and prevent electrical communication between said test contact pad and to said logic circuit in a secondary mode.    
   
   
       8 . The test device in  claim 7 , wherein said isolation circuit is configured to transition from said primary mode to said secondary mode in general correspondence with a transition from a test mode of said integrated device to a non-test mode of said integrated device.  
   
   
       9 . A circuit for a plurality of logic circuits respectively coupled to a plurality of contact pads, comprising: 
 a program circuit configured to have an initial operating characteristic and further configured to optionally permanently transition to a final operating characteristic in response to a reception by said program circuit of a program signal; and    a plurality of multiplexers coupled to said program circuit and respectively electrically interposed between said plurality of logic circuits and said plurality of contact pads, and further configured to deactivate in response to a transition to said final operating characteristic of said program circuit.    
   
   
       10 . A testing circuit for a first logic circuit and a second logic circuit, wherein said first logic circuit is coupled to a first main contact pad and a first redundant contact pad, and wherein said second logic circuit is coupled to a second main contact pad and a second redundant contact pad, comprising: 
 a program circuit configured to transmit a test mode signal before a program event and further configured to transmit a non-test mode signal after said program event;    a first test mode multiplexer coupled to said program circuit, said first logic circuit, and to said first redundant contact pad; and further configured to support electrical communication between said first logic circuit and said first redundant contact pad during a transmission of said test mode signal;    a first non-test mode multiplexer coupled to said program circuit, said first logic circuit, and to said first main contact pad; and further configured to support electrical communication between said first logic circuit and said first main contact pad during a transmission of said non-test mode signal;    a second test mode multiplexer coupled to said program circuit, said second logic circuit, and to said second redundant contact pad; and further configured to support electrical communication between said second logic circuit and said second redundant contact during said transmission of said test mode signal; and    a second non-test mode multiplexer coupled to said program circuit, said second logic circuit, and to said second main contact pad; and further configured to support electrical communication between said second logic circuit and said second main contact pad during said transmission of said non-test mode signal.    
   
   
       11 . A method of testing a logic circuit connected to a first access device, comprising: 
 connecting a second access device to said logic circuit;    examining said logic circuit through said second access device; and    electrically isolating said second access device from said logic circuit.