Single-poly non-volatile memory device

Abstract

A single-poly, P-channel non-volatile memory (NVM) cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layers on sidewalls of the gate, a P + source doping region and a P + drain doping region. The ONO layers include a first oxide layer deposited on the sidewalls of the gate and extends to the N well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer. The metallurgical junction of P-type drain and N-type well locates underneath the sidewall ONO layers.

1 . A single-poly, P-channel non-volatile memory unit, comprising: 
 a semiconductor substrate;    an N well formed in said semiconductor substrate, wherein a P+ source doping region and a P+ drain doping region are formed in said N well, a channel between said P+ source doping region and a P+ drain doping region comprises a first channel region and a second channel region that is contiguous to said first channel region and is of the same conductivity type as said first channel region;    a gate dielectric layer disposed on said first channel region;    a control gate stacked on the gate dielectric layer; and    a dielectric spacer comprising a floating charge trapping medium disposed on sidewalls of said control gate, wherein said charge trapping medium is situated directly above said second channel region, and said second channel region can be turned on or turned off by altering charge distribution in said charge trapping medium.    
   
   
       2 . The single-poly, P-channel non-volatile memory unit according to  claim 1  wherein said dielectric spacer comprises oxide-nitride-oxide (ONO) layers.  
   
   
       3 . The single-poly, P-channel non-volatile memory unit according to  claim 2  wherein said ONO layers comprise at least a silicon oxide layer and a silicon nitride layer.  
   
   
       4 . The single-poly, P-channel non-volatile memory unit according to  claim 1  wherein said single-poly, P-channel non-volatile memory unit does not include a lightly doped drain (LDD) region near the drain side.  
   
   
       5 . The single-poly, P-channel non-volatile memory unit according to  claim 1  wherein a junction between said N-type well and said P-type drain doping region is directly under said dielectric spacer for injecting electrons into said charge trapping medium.  
   
   
       6 . A single-poly, P-channel non-volatile memory unit, comprising: 
 an N well;    a gate formed on said N well;    a gate dielectric layer between said gate and said N well;    an oxide-nitride-oxide (ONO) layers disposed on sidewall of said gate, wherein said ONO layers comprise a silicon oxide layer extending from said sidewall to surface of said N well, and a silicon nitride charge trapping layer disposed on said silicon oxide layer;    a P+ drain doping region implanted into said N well next to said ONO layers such that a junction of said N-type well and said P-type drain doping region is situated directly under said ONO layers; and    a P+ source doping region, opposite to said P+ drain doping region, implanted into said N well next to said ONO layers.    
   
   
       7 . The single-poly, P-channel non-volatile memory unit according to  claim 6  wherein said gate comprises doped polysilicon.  
   
   
       8 . The single-poly, P-channel non-volatile memory unit according to  claim 6  wherein said gate dielectric layer comprises silicon oxide.  
   
   
       9 . The single-poly, P-channel non-volatile memory unit according to  claim 6  wherein said ONO layers comprise a second oxide layer on said silicon nitride charge trapping layer.  
   
   
       10 . The single-poly, P-channel non-volatile memory unit according to  claim 6  wherein said single-poly, P-channel non-volatile memory unit does not include a lightly doped drain (LDD) region.  
   
   
       11 . The single-poly, P-channel non-volatile memory unit according to  claim 6  comprising an asymmetric LDD region situated between said P+ source doping region and said gate.  
   
   
       12 . A semiconductor chip, comprising: 
 a memory array area comprising at least one single-poly, P-channel non-volatile memory unit comprising an N well; a first gate on said N well; a first gate dielectric layer between said first gate and said N well; a first oxide-nitride-oxide (ONO) layers disposed on sidewall of said first gate, wherein said first ONO layers comprises a first silicon oxide layer extending from said sidewall to surface of said N well, and a silicon nitride charge trapping layer disposed on said first silicon oxide layer; a P+ drain doping region implanted into said N well next to said first ONO layers such that a junction of said N-type well and said P-type drain doping region is situated directly under said first ONO layers; and a P+ source doping region, opposite to said P+ drain doping region, implanted into said N well next to said first ONO layers; and    a logic device area comprising at least one logic transistor device comprising a semiconductor substrate; a second gate on said semiconductor substrate; a second gate dielectric layer between said second gate and said semiconductor substrate; a second ONO layers on sidewall of said second gate; a drain doping region; a source doping region opposite to said drain doping region; and a lightly doped drain (LDD) region between said second gate and said drain doping region and between said second gate and said source doping region.    
   
   
       13 . The semiconductor chip according to  claim 12  wherein said first gate comprises doped polysilicon.  
   
   
       14 . The semiconductor chip according to  claim 12  wherein said second gate comprises doped polysilicon.  
   
   
       15 . The semiconductor chip according to  claim 12  wherein said first gate dielectric layer comprises silicon oxide.  
   
   
       16 . The semiconductor chip according to  claim 12  wherein said second gate dielectric layer comprises silicon oxide.  
   
   
       17 . The semiconductor chip according to  claim 12  wherein said first ONO layers further comprises a second silicon oxide layer on said silicon nitride charge trapping layer.