Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device formed on a first conductive type substrate is provided. The device includes a gate, a second conductive type drain region, a second conductive type source region, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region and the second conductive type source region are formed in the first conductive type substrate at both sides of the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate between the gate and the second conductive type source region.

1 . A semiconductor device, comprising: 
 a gate formed on a first conductive type substrate;    a second conductive type drain region and a second conductive type source region, formed in the first conductive type substrate at both sides of the gate; and    a second conductive type first lightly doped region formed between the gate and the second conductive type source region.    
   
   
       2 . The semiconductor device of  claim 1 , wherein the first conductive type is a P-type while the second conductive type is an N-type; or the first conductive type is an N-type while the second conductive type is a P-type.  
   
   
       3 . The semiconductor device of  claim 2 , further comprising a first dielectric layer formed between the gate and the first conductive type substrate, wherein the first dielectric layer has a first thickness at the side of the second conductive type source region and a second thickness at the side of the second conductive type drain region, and the first thickness is larger than the second thickness.  
   
   
       4 . The semiconductor of  claim 1 , further comprising a first conductive type lightly doped region formed between the gate and the second conductive type drain region.  
   
   
       5 . The semiconductor device of  claim 4 , further comprising a first dielectric layer formed between the gate and the first conductive type substrate, wherein the first dielectric layer has a first thickness at the side of the second conductive type source region and a second thickness at the side of the second conductive type drain region, and the first thickness is larger than the second thickness.  
   
   
       6 . The semiconductor of  claim 4 , further comprising a second conductive type second lightly doped region formed between the gate and the second conductive type drain region.  
   
   
       7 . The semiconductor device of  claim 6 , further comprising a first dielectric layer formed between the gate and the first conductive type substrate, wherein the first dielectric layer has a first thickness at the side of the second conductive type source region and a second thickness at the side of the second conductive type drain region, and the first thickness is larger than the second thickness.  
   
   
       8 . The semiconductor device of  claim 6 , wherein the second conductive type first lightly doped region has a dopant concentration different from the second conductive type second lightly doped region.  
   
   
       9 . The semiconductor device of  claim 1 , further comprising insulating spacers formed at the side walls of the gate.  
   
   
       10 . The semiconductor device of  claim 9 , wherein the material of the spacers comprises silicon nitride or silicon oxide.  
   
   
       11 . A method of fabricating semiconductor device, comprising: 
 providing a first conductive type substrate;    forming a gate on the first conductive type substrate;    forming a second conductive type first lightly doped region in the substrate at a first side of the gate; and    forming a second conductive type source region in the substrate at the first side of the gate, and forming a second conductive type drain region at a second side of the gate, wherein the second conductive type first lightly doped region is formed in the first conductive type substrate between the second conductive type source region and the gate.    
   
   
       12 . The method of fabricating semiconductor device of  claim 11 , wherein the first conductive type is a P-type while the second conductive type is an N-type; or the first conductive type is an N-type while the second conductive type is a P-type.  
   
   
       13 . The method of fabricating semiconductor device of  claim 11 , further comprising forming a first dielectric layer on the first conductive type substrate before the step of forming the gate on the first conductive type substrate.  
   
   
       14 . The method of fabricating semiconductor device of  claim 13 , wherein the first dielectric layer has a first thickness at the first side and a second thickness at the second side, and the second thickness is larger than the first thickness.  
   
   
       15 . The method of fabricating semiconductor device of  claim 11 , wherein the steps of forming the second conductive type first lightly doped region in the first conductive type substrate at the first side of the gate comprise: 
 forming a patterned photoresist layer exposing the first conductive type substrate at the first side of the gate on the substrate;    performing an ion implantation process to form the second conductive type first lightly doped region; and    removing the patterned photoresist layer.    
   
   
       16 . The method of fabricating semiconductor device of  claim 11 , further comprising forming a first conductive type lightly doped region in the substrate at the second side of the gate, wherein the first conductive type lightly doped region is formed between the second conductive type drain region and the gate.  
   
   
       17 . The method of fabricating semiconductor device of  claim 16 , wherein the steps of forming the second conductive type first lightly doped region in the first conductive type substrate at the first side of the gate and forming the first conductive type lightly doped region in the substrate at the second side of the gate comprise: 
 forming a first patterned photoresist layer exposing the first conductive type substrate at the first side of the gate on the substrate;    performing a first ion implantation process to form the second conductive type first lightly doped region;    removing the first patterned photoresist layer;    forming a second patterned photoresist layer exposing the first conductive type substrate at the second side of the gate on the substrate;    performing a second ion implantation process to form the first conductive type lightly doped region; and    removing the second patterned photoresist layer.    
   
   
       18 . The method of fabricating semiconductor device of  claim 16 , further comprising: forming a second conductive type second lightly doped region in the substrate at the second side of the gate, wherein the second conductive type second lightly doped region is formed between the second conductive type drain region and the gate.  
   
   
       19 . The method of fabricating semiconductor device of  claim 18 , wherein the steps of forming the second conductive type first lightly doped region and the second conductive type second lightly doped region in the first conductive type substrate at the first side and the second side of the gate and forming the first conductive type lightly doped region in the substrate at the second side of the gate comprise: 
 performing a first ion implantation process to form the second conductive type first lightly doped region and the second conductive type second lightly doped region;    forming a patterned photoresist layer exposing the first conductive type substrate at the second side of the gate on the substrate;    performing a second ion implantation process to form the first conductive type lightly doped region; and    removing the patterned photoresist layer.    
   
   
       20 . The method of fabricating semiconductor device of  claim 11 , further comprising forming insulating spacers at the side walls of the gate.