Resistive memory devices including selected reference memory cells and methods of operating the same

Abstract

A method of accessing a resistive memory device can include applying a predetermined voltage level to a first word line coupled to a first resistive memory cell block during a read operation of a second resistive memory cell block coupled to a second word line, A programming current can be conducted via a pair of opposing current source transistors located on first and second opposing sides of the first block to provide the programming current from the first end to the second end across bit lines coupled to resistive memory cells in the first block and to provide the programming current parallel to the second block.

1 . A method of accessing a resistive memory device comprising: 
 applying a predetermined voltage level to a first word line coupled to a first resistive memory cell block during a read operation of a second resistive memory cell block coupled to a second word line; and    conducting programming current via a pair of opposing current source transistors located on first and second opposing sides of the first block to conduct the programming current from the first end to the second end across bit lines coupled to resistive memory cells in the first block and to conduct the programming current parallel to the second block.    
   
   
       2 . A method according to  claim 1  wherein the predetermined voltage level comprises a first voltage level, the method further comprising: 
 applying a second voltage level to the second word line, wherein the second voltage level is greater than or less than the first voltage level.    
   
   
       3 . A method according to  claim 2  further comprising: 
 applying the first voltage level to a bit line coupled to the second block.    
   
   
       4 . A method according to  claim 1 , wherein either the first voltage level or the second voltage level is a ground level.  
   
   
       5 . A magnetic memory cell array device comprising: 
 a first current source line extending between pluralities of first and second memory cells configured for respective simultaneous programming and configured to conduct adequate programming current for writing one of the pluralities of first and second memory cells;    a first current source transistor coupled to the first current source line and to a word line;    a programming conductor coupled to the first current source transistor and extending across bit lines coupled to the one of the pluralities of first and second memory cells, configured to conduct the programming current across the bit lines;    a second current source transistor coupled to the programming conductor and configured to switch the programming current from the programming conductor to a second current source transistor output;    a second current source line extending adjacent the one of the pluralities of first and second memory cells opposite the first current source line;    a first bias circuit configured to apply a first bias voltage to the first or second memory cells selected for accessed during a read operation; and    a second bias circuit configured to apply a second bias voltage to the first or second memory cells unselected for access during the read operation.    
   
   
       6 . A magnetic memory cell array according to  claim 5  further comprising: 
 a bit line driver circuit configured to provide a third bias voltage to the first or second memory cells unselected for access during the read operation, the third bias voltage being substantially equal to the second bias voltage.    
   
   
       7 . A magnetic memory cell array according to  claim 6  further comprising: 
 first and second pass transistors each coupled between respective outputs of the first and second bias circuits and the first and second word lines; and    first and second enable gates coupled to gates of the first and second pass transistors, configured to pass the predetermined voltage level from the respective outputs to the first and second word lines through the pass transistors responsive to outputs of the enable gates.    
   
   
       8 . A magnetic memory cell array according to  claim 7  wherein the first and second pass transistors each provide a single voltage drop across respective devices between the outputs and the first word line.  
   
   
       9 . A magnetic memory cell array according to  claim 5 , wherein the magnetic memory cell array is included in a personal media player, mobile navigation system, home appliance, personal digital assistance, personal computer, digital camera, television, or game console.  
   
   
       10 . A magnetic memory cell array according to  claim 5 , wherein the first and second word lines comprises respective first and second digit lines.  
   
   
       11 . A method of reading data from a resistive memory device comprising: 
 applying a predetermined voltage level to a first word line coupled to a first resistive memory cell during a read operation of a second resistive memory cell coupled to a second word line.    
   
   
       12 . A method according to  claim 11  wherein the predetermined voltage level comprises a first voltage level, the method further comprising: 
 applying a second voltage level to the second word line, wherein the second voltage level is greater than or less than the first voltage level.    
   
   
       13 . A method according to  claim 12  further comprising: 
 applying the first voltage level to a bit line coupled to the second resistive memory cell.    
   
   
       14 . A method according to  claim 11  further comprising: 
 applying a voltage level that is substantially equal to the predetermined voltage level to a bit line coupled to the first resistive memory cell, wherein the read operation comprises a single memory cell read operation.    
   
   
       15 . A method according to  claim 11  wherein the read operation comprises a simultaneous read operation of a plurality of resistive memory cells coupled to the second word line.  
   
   
       16 . A method of writing data to a resistive memory device comprising: 
 conducting programming current via a pair of opposing current source transistors located on first and second opposing sides of a block of resistive memory cells to conduct the programming current from the first end to the second end across bit lines coupled to the resistive memory cells and to conduct the programming current parallel to at least one block of resistive memory cells located adjacent the first or second end.    
   
   
       17 . A method according to  claim 16  wherein the resistive memory cells comprise magnetic memory cells, PRAM cells, or OxRam cells.  
   
   
       18 . A method of providing programming current to resistive memory cells during a write operation to a resistive memory device, the method comprising: 
 conducting programming current across bit lines in a block of resistive memory cells to be programmed while avoiding conducting the programming current across bit lines included in adjacent blocks of the resistive memory cells.    
   
   
       19 . A method according to  claim 18  wherein the resistive memory cells comprise magnetic memory cells, PRAM cells, or OxRam cells.  
   
   
       20 . A resistive memory device comprising: 
 a pair of opposing current source transistors located at respective first and second ends of a block of memory cells and configured to conduct programming current from the first to the second ends across bit lines coupled to the memory cells and configured to conduct the programming current parallel to adjacent blocks of memory cells.    
   
   
       21 . A method according to  claim 20  wherein the resistive memory cells comprise magnetic memory cells, PRAM cells, or OxRam cells.  
   
   
       22 . A resistive memory device comprising: 
 a bias circuit configured to apply a predetermined voltage level to a first word line coupled to a first resistive memory cell during a read operation of a second resistive memory cell coupled to a second word line.    
   
   
       23 . A device according to  claim 22 , wherein the predetermined voltage level is a ground level.  
   
   
       24 . A device according to  claim 22 , wherein the resistive memory device is included in a personal media player, mobile navigation system, home appliance, personal digital assistance, personal computer, digital camera, television, or game console.  
   
   
       25 . A device according to  claim 22  wherein the bias circuit comprises a first bias circuit, the device further comprising: 
 a second bias circuit configured to apply a second voltage level to a word line coupled to the second resistive memory cell, wherein the second voltage level is greater than or less than the first voltage level.    
   
   
       26 . A device according to  claim 22  further comprising: 
 a pass transistor coupled between an output of the bias circuit and the first word line; and    an enable gate coupled to a gate of the pass transistor, configured to pass the predetermined voltage level from the output to the first word line through the pass transistor responsive to an output of the enable gate.    
   
   
       27 . A device according to  claim 26  wherein the pass transistor comprises the only voltage drop across a device between the output and the first word line.  
   
   
       28 . A device according to  claim 22  further comprising: 
 a pass transistor coupled to the output and configured to provide the output to a drain bias line; and    a low switching transistor coupled to the drain bias line and configured to provide the output to the first word line responsive to a row address decoder enable signal.    
   
   
       29 . A resistive memory device comprising: 
 a first bias circuit configured to apply a first bias voltage to first or second memory cells selected for accessed during a read operation; and    a second bias circuit configured to apply a second bias voltage to the first or second memory cells unselected for access during the read operation.    
   
   
       30 . A resistive memory device having a plurality of cell blocks, each cell block comprising: 
 a plurality of bitlines;    a plurality of bottom electrodes crossing over the bitlines;    a plurality of resistive cells being located in cross points of the bottom electrodes and the bitlines, each of the resistive cells having a first electrode coupled to one of the bitlines and has a second electrode coupled to one of the bottom electrodes;    a plurality of digitlines corresponding to each of the bottom electrodes;    a plurality of switching transistors being coupled to the digitlines and bottom electrodes; and    a cell block select line coupled to an input node of the switching transistors, wherein at least one digitline is coupled to each cell block in common.    
   
   
       31 . A device according to  claim 30  further comprising: 
 a column decoder being coupled to the cell block select line; and    a row decoder being coupled to a plurality of the digitlines, the row decoder providing a selected digitline with a first voltage level and unselected digitlines with a second voltage level; and    a sense amplifier circuit being coupled to the bitlines, the sense amplifier providing the selected bitline with the second voltage level and sensing a current through the selected bitlines.    
   
   
       32 . A device according to  claim 31 , wherein either the first voltage level or the second voltage level is ground level.