Cross diffusion barrier layer in gate structure

Abstract

Various embodiments include a substrate having including a first doped region and a second doped region located on a first side of the substrate, and a third doped region and a fourth doped region located on a second side of the substrate, an insulation layer overlying the substrate, a gate layer overlying the insulation layer, a barrier layer overlying the gate layer, and an electrode layer overlying the barrier layer. The first and third doped regions may be located on a first side of the gate layer. The second and fourth doped regions may be located on a second side of the gate layer. The first and third doped regions may be source and drain regions of a first transistor. The second and fourth doped regions may be source and drain regions of a second transistor. The gate layer may include a gate segment to couple to a third transistor. Other embodiments are disclosed.

1 . A device comprising: 
 a substrate including a first doped region and a second doped region located on a first side of the substrate, and a third doped region and a fourth doped region located on a second side of the substrate;    an insulation layer overlying the substrate;    a gate layer overlying the insulation layer, wherein the first and third doped regions are located on a first side of the gate layer, wherein the second and fourth doped regions are located on a second side of the gate layer, wherein the first and third doped regions are source and drain regions of a first transistor, wherein the second and fourth doped regions are source and drain regions of a second transistor, and wherein the gate layer includes a gate segment to couple to a third transistor;    a barrier layer overlying the gate layer; and    an electrode layer overlying the barrier layer.    
   
   
       2 . The device of  claim 1 , wherein the barrier layer includes nitrogen.  
   
   
       3 . The device of  claim 2 , wherein the barrier layer includes silicon combined with the nitrogen.  
   
   
       4 . The device of  claim 1 , wherein the barrier layer has a thickness in a range of about 5 angstroms to about 10 angstroms.  
   
   
       5 . The device of  claim 1 , wherein the barrier layer includes about 10 percent to about 40 percent nitrogen.  
   
   
       6 . The device of  claim 1 , wherein the at least one of the first, second, third, and fourth doped regions are doped with a dopant, and wherein the dopant is one of arsenic, phosphorous, and boron.  
   
   
       7 . The device of  claim 1 , wherein the gate layer includes a first gate portion, and a second gate portion coupled to the first gate portion, wherein the first gate portion having a first conductivity type, and wherein the second gate portion having a second conductivity.  
   
   
       8 . The device of  claim 1 , wherein the electrode layer includes one of tungsten silicide, titanium silicide, and tungsten nitride.  
   
   
       9 . A device comprising: 
 a first transistor coupled to a substrate, the first transistor including a first source and a first drain; and    a second transistor coupled to the first transistor, the second transistor including a second source and a second drain, the first and second transistors sharing a gate structure, the gate structure including:    a polysilicon layer, wherein the first source and the second drain are located on a first side of the polysilicon layer, wherein the first drain and the second source are located on a second side of the polysilicon layer, and wherein the polysilicon layer including a segment to couple to one of a source and a drain of a third transistor;    an electrode layer overlying the polysilicon layer; and    a barrier layer sandwiched between the electrode layer and the polysilicon layer.    
   
   
       10 . The device of  claim 9 , wherein the first transistor includes a p-channel transistor.  
   
   
       11 . The device of  claim 10 , wherein the second transistor includes an n-channel transistor.  
   
   
       12 . The device of  claim 9 , wherein the barrier layer includes a combination of silicon and nitrogen.  
   
   
       13 . The device of  claim 12 , wherein the electrode layer includes tungsten silicide.  
   
   
       14 . The device of  claim 9 , wherein the barrier layer has a thickness of about one percent of a thickness of the gate layer.  
   
   
       15 . A device comprising: 
 a first inverter; and    a second inverter coupled to the first inverter via a first storage node and at a second storage node, each of the first and second inverters including a first transistor, and a second transistor coupled to the first transistor, and a gate structure shared by the first and second transistors, the gate structure including:    a gate layer, wherein a source of the first transistor and a drain of the second transistor are located on a first side of the gate layer, and wherein a drain of the first transistor and a source of the second transistor are located on a second side of the gate layer;    an electrode layer; and    a barrier layer sandwiched between the electrode layer and the polysilicon layer, wherein the gate layer of the gate structure of the first inverter includes a segment to couple to a third transistor, and wherein the gate layer of the gate structure of the second inverter includes a segment to couple to a fourth transistor.    
   
   
       16 . The device of  claim 15 , wherein the first inverter includes an input coupled to the first storage node and an output coupled to the second storage node, and wherein the second inverter includes an input coupled to the second storage node and an output coupled to the first storage node.  
   
   
       17 . The device of  claim 16 , wherein the third transistor includes a source coupled to the first storage node, a drain coupled to a first bit line, and a gate coupled to a word line, and wherein the fourth transistor includes a source coupled to the second storage node, a drain coupled to a second bit line, and a gate coupled to the word line.  
   
   
       18 . The device of  claim 15 , wherein the barrier layer includes a combination of silicon and nitrogen.  
   
   
       19 . The device of  claim 15 , wherein the barrier layer has a thickness of about a thickness of a nitrogen atom.  
   
   
       20 . The device of  claim 18 , wherein the electrode layer includes tungsten nitride.  
   
   
       21 . A system comprising: 
 a processor; and    a static random access memory device coupled to the processor, the static random access memory device including:    a substrate including a first doped region and a second doped region located on a first side of the substrate, and a third doped region and a fourth doped region located on a second side of the substrate;    an insulation layer overlying the substrate;    a gate layer overlying the insulation layer, wherein the first and third doped regions are located on a first side of the gate layer, wherein the second and fourth doped regions are located on a second side of the gate layer, wherein the first and third doped regions are source and drain regions of a first transistor, wherein the second and fourth doped regions are source and drain regions of a second transistor, and wherein the gate layer includes a gate segment to couple to a third transistor;    a barrier layer overlying the gate layer; and    an electrode layer overlying the barrier layer.    
   
   
       22 . The system of  claim 21 , wherein the barrier layer includes nitrogen.  
   
   
       23 . The system of  claim 22 , wherein the barrier layer includes silicon combined with the nitrogen.  
   
   
       24 . The system of  claim 23 , wherein the electrode layer titanium silicide.  
   
   
       25 . The system of  claim 24 , wherein the barrier layer includes about 80 percent of silicon and about 20 percent of nitrogen.