Serial data input/output method and apparatus

Abstract

A serial scan path communication architecture includes a plurality of circuits ( 30 ), some of which may include a memory ( 36 ). A memory access controller ( 38 ) is included in circuits with a memory ( 36 ) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple TAP read or write operations.

1 . A data communication interface operable to communicate with a device, comprising: 
 bus circuitry for transferring data;    storage circuitry coupled to the device and to said bus;    interface circuitry operable to shift data between said bus and said storage circuitry; and    device access control circuitry operable to transfer data between said device and said storage circuitry responsive to a control signal.    
   
   
       2 . The data communication interface of  claim 1  wherein said device comprises a memory.  
   
   
       3 . The data communication interface of  claim 1  wherein said storage circuitry comprises a register.  
   
   
       4 . The data communication interface of  claim 3  wherein said storage circuitry comprises a shift register.  
   
   
       5 . The data communication interface of  claim 4  wherein said interface circuitry is operable to shift data from said bus circuitry to said shift register and from said shift register to said bus circuitry.  
   
   
       6 . The data communication interface of  claim 5  and further comprising a plurality of shift registers coupled to said bus circuitry.  
   
   
       7 . The data communication interface of  claim 6  wherein said interface circuitry is operable to shift data between said bus circuitry and a selected one of said shift registers.  
   
   
       8 . The data communication interface of  claim 1  wherein said device access control is operable to transfer data between said device and said storage circuitry responsive to a signal from said interface circuitry.  
   
   
       9 . The data communication interface of  claim 8  wherein said device access control is operable to transfer data between said device and said storage circuitry responsive to a pause signal from said interface circuitry.  
   
   
       10 . The data communication interface of  claim 1  wherein said device access control is operable to transfer data between said device and said storage circuitry responsive to receiving a predetermined sequence of data.  
   
   
       11 . The data communication interface of  claim 10  wherein said device access control includes: a first register for receiving and storing data; a second register for storing said predetermined sequence of data; and compare circuitry for generating a signal responsive to a match between the data stored in said first and second registers.  
   
   
       12 . The data communication interface of  claim 1  wherein said device access control is operable to transfer data between said device and said storage circuitry responsive to signal indicating that a counter has counted to a predetermined number.  
   
   
       13 . The data communication interface of  claim 12  wherein said device access controller includes: a counter coupled to said bus circuitry and operable to increment a value stored therein responsive to a clocking signal; circuitry to output a control signal responsive to said counter storing a predetermined value.  
   
   
       14 . The data communication interface of  claim 12  wherein said device access controller includes: a counter coupled to said bus circuitry and operable to decrement a value stored therein responsive to a clocking signal; circuitry to output a control signal responsive to said counter storing a predetermined value.  
   
   
       15 . The data communication interface of  claim 1  and further comprising a bus controller coupled to said bus and operable transmit data thereon.  
   
   
       16 . The data communication interface of  claim 15  wherein said bus controller is further operable to receive data from said bus.  
   
   
       17 . A data communication interface operable to communicate with a device, comprising: 
 bus circuitry for transferring data;    storage circuitry coupled to said bus circuitry and operable to selectively shift data in from said bus circuitry and shift data out to said bus circuitry;    device interface circuitry operable to control data transfer between said bus circuitry and said storage circuitry; and    device access control circuitry operable to control data transfer between said bus circuitry and said storage circuitry such that data can be written to or read from the device without the need to repetitively cycle through multiple shift operations.    
   
   
       18 . The data communication interface of  claim 17  wherein said device access control circuitry is operable to write data to the device responsive to one or more control signal.  
   
   
       19 . The data communication interface of  claim 18  wherein said one of said control signals is generated by said device interface circuitry.  
   
   
       20 . The data communication interface of  claim 19  wherein said device interface circuitry comprises a state machine and one or more of said control signals are associated with predetermined states of the state machine.