Efficient Utilization of Shared Buffer Memory and Method for Operating the Same

Abstract

Broadly speaking, an apparatus for efficiently utilizing a shared packet buffer memory in a switch and a method for operating the same is provided. More specifically, the apparatus includes a memory having a number of buffers configured to be operated in a ratcheted manner. The ratcheted manner in which the memory is operated causes each incoming data stream to be distributed across the number of buffers. Each stored data stream can also be retrieved from the number of buffers for output from the memory in a similar ratcheted manner. The memory uses a rotating selector to control the ratcheted manner of operation. Also, the memory is capable of simultaneously servicing each of a number of inputs and a number of outputs to which the memory is connected.

1 . A ratcheting distributor for distributing a data stream across a number of memory banks, comprising: 
 a number of multiplexers, each of the number of multiplexers configured to receive a number of inputs, each of the number of multiplexers having an output connected to one of the number of memory banks such that one of the number of multiplexers is connected to each of the number of memory banks, each of the number of multiplexers further configured to receive one of a number of selector signals capable of controlling which of the number of inputs will be transmitted to the output, each of the number of selector signals being defined by a different ordering of a number of individual signals, the number of individual signals being equal to the number of inputs;    a rotating selector capable of generating the number of individual signals, the rotating selector causing one of the number of individual signals to have a first digital state and each of the remaining number of individual signals to have a second digital state on a given clock cycle, the rotating selector further causing the first digital state to be rotated among the number of individual signals on successive clock cycles; and    a clock for exercising the rotating selector.