Semiconductor memory device

Abstract

A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA [ 2 ], and a storage block is selected with external address bit AA [ 23 ]. Upper word data LW and lower word data UW are compressed into byte data of 8 bits, respectively, and stored in a memory cell array.

1 .- 13 . (canceled)  
   
   
       14 . A semiconductor memory device comprising: 
 a plurality of memory cells aligned in rows and columns;    a plurality of reference cells;    an averaging circuit for averaging currents flowing through said plurality of reference cells; and    a current/voltage conversion circuit for converting a current generated by said averaging circuit to a voltage to generate a reference voltage.    
   
   
       15 . The semiconductor memory device according to  claim 14 , further comprising: 
 a sense amplifier for generating a comparison current in accordance with said reference voltage and comparing the comparison current with a current flowing through a selected memory cell in said plurality of memory cells to detect data of the selected memory cell.    
   
   
       16 . The semiconductor memory device according to  claim 14 , wherein 
 said plurality of reference cells is aligned in rows and columns, and    said semiconductor memory device further comprises a selection circuit for selecting reference cells in said plurality of reference cells in accordance with an operation mode and coupling selected reference cells to said averaging circuit.    
   
   
       17 . The semiconductor memory device according to  claim 14 , wherein said reference cells are the same in structure as the memory cells and each reference cell has a transistor structure having a control gate and a floating gate connected together.  
   
   
       18 . The semiconductor memory device according to  claim 14 , wherein 
 the reference cells comprise an insulating gate type field effect transistor having a size set in accordance with a level of the reference voltage to be generated.    
   
   
       19 . A semiconductor memory device, comprising: 
 a plurality of memory cells aligned in rows and columns;    a plurality of word lines arranged corresponding to the memory cell rows, and connecting to the memory cells in corresponding rows;    a circuit for generating a first voltage at a predetermined voltage level to be transmitted onto a selected word line in said plurality of word lines;    a division circuit for generating a divided voltage by dividing said first voltage;    a reference cell selectively rendered conductive in accordance with a divided voltage;    a reference voltage generation circuit for generating a reference voltage in accordance with a current flowing said reference cell; and    a sense amplifier circuit for generating a comparison reference current in accordance with the reference voltage generated by said reference voltage generation circuit and comparing the comparison current with a current flowing through a selected memory cell to detect memory cell data in accordance with a result of comparison.    
   
   
       20 . The semiconductor memory device according to  claim 19 , wherein 
 said reference cell is the same in structure as the memory cells and has a transistor structure having a control gate and a floating gate interconnected.    
   
   
       21 . The semiconductor memory device according to  claim 19 , wherein 
 said reference cell includes an insulating gate type field effect transistor having a size set in accordance with a level of the reference voltage to be generated.    
   
   
       22 - 25 . (canceled)