Semiconductor storage device, redundancy circuit thereof, and portable electronic device

Abstract

A semiconductor storage device includes a plurality of memory elements and a redundancy circuit. Each of the memory elements includes a gate electrode provided on a semiconductor layer, a gate insulating film intervening between the gate electrode and the semiconductor layer, a channel region provided under the gate electrode, diffusion regions respectively provided at both sides of the channel region, the diffusion regions having a conductivity type which is opposite a conductivity type of the channel region, and memory functioning members respectively provided at both sides of the gate electrode, the memory functioning members having a function of holding charge. The redundancy circuit addresses a single chip memory including cells associated with a plurality of redundant lines and includes a decoder for selecting a redundant row. The semiconductor storage device can permanently inactivate further programming of the redundancy circuit in order to prevent a user from performing inadvertent programming.

1 . A redundancy circuit provided in a semiconductor storage device including a plurality of memory elements, first lines selected by first address signals, second lines selected by second address signals, a plurality of array decoders which receive the first address signals, and a plurality of array lines selected by the array decoders, wherein: 
 each of the plurality of memory elements includes 
 a gate electrode provided on a semiconductor layer, a gate insulating film intervening between the gate electrode and the semiconductor layer,  
 a channel region provided under the gate electrode,  
 diffusion regions respectively provided at both sides of the channel region, the diffusion regions having a conductivity type which is opposite a conductivity type of the channel region, and  
 memory functioning members respectively provided at both sides of the gate electrode, the memory functioning members having a function of holding charge,  
   the redundancy circuit comprising 
 a plurality of redundant lines,  
 a plurality of redundant decoders for selecting the redundant lines, the redundant decoders being connected to the array decoders so as to prevent selection of the array lines upon selection of one of the redundant lines,  
 programmable gate means which receives the first address signals, the programmable gate means being programmed so as to supply predetermined ones of the first address signals to the redundant decoders,  
   selecting means which receives the second address signals, the second address signals being for selecting the programmable gate means during programming of the programmable gate means, and    preventing means for preventing the programming of the programmable gate means, the preventing means being activated by predetermined ones of the second address signals.    
   
   
       2 . The redundancy circuit as set forth in  claim 1 , wherein: 
 the programmable gate means includes 
 a fuse, and  
 two transistors serially connected to the fuse and connected to each other in parallel, one of the two transistors having a threshold voltage of substantially zero volts; and  
   the programming being performed by blowing the fuse through the transistors.    
   
   
       3 . The redundancy circuit as set forth in  claim 1 , wherein: 
 the programmable gate means includes a polysilicon fuse which is selectively blown.    
   
   
       4 . The redundancy circuit as set forth in  claim 3 , wherein: 
 blowing of the polysilicon fuse controls selection of true and complement ones of the first address signals.    
   
   
       5 . The redundancy circuit as set forth in  claim 1 , wherein: 
 the preventing means includes a polysilicon fuse which is blown so as to prevent the programming.    
   
   
       6 . A redundancy circuit as set forth in  claim 1 , further comprising: 
 deselecting means for deselecting a defective one of the redundant lines.    
   
   
       7 . A semiconductor storage device, comprising: 
 a plurality of memory elements including 
 a gate electrode provided on a semiconductor layer, a gate insulating film intervening between the gate electrode and the semiconductor layer,  
 a channel region provided under the gate electrode,  
 diffusion regions respectively provided at both sides of the channel region, the diffusion regions having a conductivity type which is opposite a conductivity type of the channel region, and  
 memory functioning members respectively provided at both sides of the gate electrode, the memory functioning members having a function of holding charge;  
   first lines selected by first address signals;    second lines selected by the second address signals; and    the redundancy circuit as set forth in  claim 1 ,    the memory functioning member of the memory element including a film whose surface is substantially parallel to a surface of the gate insulating film, the film having a function of holding charge.    
   
   
       8 . A portable electronic device including the semiconductor device as set forth in  claim 7.