Metal during pattern for memory devices

Abstract

A memory integrated circuit having three layers of metallic traces disposed over a substrate assembly including various active devices. The traces are arranged to include I/O traces that are continuous in the third layer across spans of 4 or 8 memory blocks of an array, and that are interspersed on the third layer with non-I/O lines adapted to reduce interference between I/O lines. Column select lines, orthogonal to I/O lines and disposed in the third layer of metallic traces, except in the vicinity of I/O lines, are provided in a linear configuration and shielded from parallel digit lines in the first layer of traces by traces of the intervening second layer of traces. Global bleeder lines disposed in the third layer of traces are adapted to apply a standby voltage to a plurality of sense amplifiers. Other features of the invention include two layer power and ground bus traces, and row decoder and phase driver circuits disposed in throat and gap cell regions respectively.

1 - 6 . (canceled)  
   
   
       7 . An integrated circuit memory device comprising: 
 a substrate assembly including a memory array;    said memory array including a plurality of memory blocks, at least eight of said memory blocks being arranged in spaced relation to one another in a first direction relative to said substrate assembly;    a sense amplifier stripe having a longitudinal axis oriented substantially parallel to said first direction;    first, second, and third layers of metallic traces disposed in substantially parallel spaced relation over said substrate assembly; and    an I/O trace disposed among said traces of one of said layers having a longitudinal axis oriented substantially parallel to said first direction.    
   
   
       8 . A device as in  claim 7  wherein said I/O trace spans at least four of said eight memory blocks.  
   
   
       9 . A device as in  claim 7  wherein said I/O trace spans at least eight of said memory blocks.  
   
   
       10 - 14 . (canceled)  
   
   
       15 . An integrated circuit memory device comprising: 
 a substrate assembly;    a layer of metallic traces including a local phase line trace;    a pair of wordline driver circuits, each of said circuits including one transistor of a pair of transistors formed within a common active region of said substrate assembly, said transistors sharing a common drain, said drain having a single connection to said local phase line trace.    
   
   
       16 . An integrated circuit memory device comprising: 
 a substrate assembly;    at least first, second, and third layers of metallic traces disposed in substantially parallel spaced relation over said substrate assembly;    a global bleeder circuit disposed within said substrate assembly and adapted to supply a standby voltage; and    a sense amplifier circuit disposed within said substrate assembly;    a global bleeder trace, at least a portion of which is disposed among said traces of said third layer of traces, operatively connected to both said bleeder circuit and said sense amplifier, and adapted to communicate said standby voltage from said bleeder circuit to said sense amplifier.    
   
   
       17 - 45 . (canceled)