Semiconductor device and manufacturing method of the same

Abstract

This invention miniaturizes a package of a semiconductor device and simplifies a manufacturing procedure to reduce a manufacturing cost. A semiconductor wafer formed of a plurality of semiconductor chips formed with MEMS devices and wiring thereof on front surface thereof and a cap arrayed wafer disposed with a plurality of sealing caps are attached to seal the MEMS devices in cavities between them. Then, a plurality of via-holes is provided penetrating through the semiconductor wafer to form embedded electrodes therein, and bump electrodes are formed thereon. After this procedure, this structure is cut along scribe lines to be divided into each of packages.

1 - 10 . (canceled)  
   
   
       11 . A method of manufacturing a semiconductor device, comprising: 
 providing a semiconductor wafer comprising a plurality of device areas that are defined by scribe lines, each of the device areas comprising device elements formed on a surface of the semiconductor wafer;    providing a cap arrayed wafer that includes a plurality of concave portions formed therein;    attaching the semiconductor wafer and the cap arrayed wafer so that the device elements of a device area of the semiconductor wafer are sealed in a corresponding concave portion of the cap arrayed wafer; and    dividing along the scribe lines the attached semiconductor wafer and the cap arrayed wafer into individual packages.    
   
   
       12 . the method of  claim 11 , wherein the device elements of the device area are sealed in vacuum.  
   
   
       13 . The method of  claim 11 , wherein the device elements of the device area are sealed in an inert gas.  
   
   
       14 . The method of  claim 11 , further comprising forming a metal thin film on inner surfaces of the concave portions so as to provide a filter function of blocking or transmitting light having a predetermined wavelength.  
   
   
       15 . The method of  claim 11 , further comprising forming a via-hole in the device area, forming an embedded electrode in the via-holes, and forming a wiring connecting the embedded electrode and at least one of the device elements.  
   
   
       16 . The method of  claim 11 , further comprising back-grinding the semiconductor wafer after attaching the cap arrayed wafer and the semiconductor wafer.  
   
   
       17 . The method of  claim 11 , further comprising back-grinding the cap arrayed wafer after attaching the cap arrayed wafer and the semiconductor wafer.  
   
   
       18 . The method of  claim 11 , further comprising back-grinding the semiconductor wafer and the cap arrayed wafer after attaching the cap arrayed wafer and the semiconductor wafer.