High resistance cmos resistor

Abstract

A high resistance CMOS resistor with a relatively small die size is provided. The CMOS resistor includes a p-field region disposed in a n-well of a substrate and a pair of p-type contact regions respectively disposed beside a field oxide layer in the n-well. The pair of p-type contact regions are respectively connected to two sides of the p-field region as a first ohmic contact and a second ohmic contact for the CMOS resistor. The CMOS resistor according to the present invention has a resistance of, for example, 10 kΩ-20 kΩ per square.

1 . A semiconductor structure of a CMOS resistor, comprising: 
 a p-type silicon substrate;    an n-well disposed in the p-type silicon substrate;    a p-well disposed in a non-active area of the p-type silicon substrate;    a first p-field region disposed in the p-well;    a second p-field region disposed in the n-well;    a field oxide layer disposed on the first p-field region and the second p-field region;    an n-type contact region disposed in the n-well; and    a pair of two p-type contact regions respectively disposed beside the field oxide layer in the n-well as a first ohmic contact and a second ohmic contact.    
   
   
       2 . The semiconductor structure according to  claim 1 , further comprising a patterned BPSG layer formed to build two contact openings exposing a portion of the n-type contact region and the two p-type contact regions.  
   
   
       3 . The semiconductor structure according to  claim 2 , further comprising two metal contact plugs disposed in the contact openings to electrically connect to the first ohmic contact and the second ohmic contact of the CMOS resistor.  
   
   
       4 . The semiconductor structure according to  claim 3 , further comprising a passivation layer deposited over the contact plugs covering the CMOS resistor.  
   
   
       5 . The semiconductor structure according to  claim 1 , wherein the CMOS resistor is formed compatibly with a standard CMOS process.  
   
   
       6 . A semiconductor structure of a CMOS resistor, comprising: 
 an n-well;    a first p-type contact region disposed in the n-well;    a second p-field region coupled to the first p-type contact region;    a second p-type contact region coupled to the second p-field region; and    a field oxide layer formed on the second p-field region.    
   
   
       7 . The semiconductor structure according to  claim 6 , further comprising an n-type contact region coupled to the first p-type contact region.  
   
   
       8 . The semiconductor structure according to  claim 6 , further comprising a p-well coupled to the n-well.  
   
   
       9 . The semiconductor structure according to  claim 8 , further comprising a first p-field region formed on the p-well.  
   
   
       10 . The semiconductor structure according to  claim 9 , further comprising a field oxide layer formed on the second p-field region.  
   
   
       11 . A CMOS resistor, comprising: 
 a p-field region disposed in a n-well of a substrate; and    a pair of p-type contact regions respectively disposed beside a field oxide layer in the n-well, wherein the pair of p-type contact regions are respectively connected to two sides of the p-field region as a first ohmic contact and a second ohmic contact for the CMOS resistor.