Semiconductor device and method for fabricating the same

Abstract

Methods for forming semiconductor memory structures including air gaps between adjacent gate structures are provided. The volume of the air gaps is maximized and the width thereof made uniform in order to minimize the parasitic capacitance and any variance therein between the gate structures. The methods include forming an insulation layer between adjacent gate structures and subsequently etching the insulation layer to leave an air gap. Devices fabricated in accordance with the methods are also provided.

1 . A semiconductor device comprising: 
 at least two adjacent gate structures disposed on a semiconductor substrate, the at least two adjacent gate structures having an air gap defined therebetween, the air gap being substantially rectangular in cross-section.    
   
   
       2 . The device of  claim 1 , wherein the air gap is formed self-aligned with opposing sidewalls of the at least two gate structures.  
   
   
       3 . A semiconductor device comprising: 
 at least two adjacent cell gate structures disposed on a semiconductor substrate, the cell gate structures adapted to store a charge; and    a protection layer disposed on opposing sidewalls of the at least two adjacent gate structures, the protection layer defining an air gap between the at least two adjacent cell gate structures, the protection layer having opposing vertical portions, each disposed between the air gap and the opposing sidewalls of the at least two adjacent gate structures, and a horizontal portion, disposed between the air gap and the semiconductor substrate, the vertical portion having a substantially uniform thickness.    
   
   
       4 . The device of  claim 3 , wherein the horizontal portion of the protection layer is formed conformally on the semiconductor substrate so as to have a substantially uniform thickness.  
   
   
       5 . The device of  claim 3 , wherein the vertical portion of the protection layer has an inner sidewall and an outer sidewall opposite the inner sidewall, the outer sidewall adjoining the sidewalls of the gate structures, the inner sidewall being substantially parallel with the sidewalls of the gate structures.  
   
   
       6 . The device of  claim 3 , wherein the thickness of the vertical portion is substantially equal to the thickness of the horizontal portion.  
   
   
       7 . The device of  claim 3 , wherein the gate structures each comprise a tunneling dielectric pattern, a charge-storage layer, an inter-gate dielectric, a control gate, which are sequentially stacked, the air gap extending between adjacent charge-storage layers.  
   
   
       8 . The device of  claim 7 , wherein the charge-storage layer is a charge-trap dielectric layer or a polysilicon floating gate.  
   
   
       9 . The device of  claim 3 , wherein the gate structures include a tunnel oxide layer, a nitride layer, another oxide layer, and a polysilicon layer, which are sequentially formed, to form a SONOS cell gate structure.  
   
   
       10 . The device of  claim 3 , wherein the gate structures include a tunnel oxide layer, a nitride layer, an Al 2 O 3  layer, and a TaN layer, which are sequentially formed, to form a TANOS cell gate structure.  
   
   
       11 . The device of  claim 3 , wherein the gate structures include a tunnel oxide layer, a nitride layer, an Al 2 O 3  layer, and a polysilicon layer, which are sequentially formed, to form a SANOS cell gate structure.  
   
   
       12 . The device of  claim 3 , further comprising an interlayer insulation layer sealing the air gap.  
   
   
       13 . The device of  claim 12 , wherein a bottom portion of the interlayer insulation layer directly overlies a top of the air gap.  
   
   
       14 . The device of  claim 2 , wherein an inner sidewall of the vertical portion and a top surface of the horizontal portion form an approximately 90 degree angle.  
   
   
       15 . A semiconductor device comprising: 
 at least two adjacent memory cell gate structures disposed on a semiconductor substrate, the at least two adjacent memory cell gate structures having an air gap disposed therebetween, the air gap having a substantially uniform width over its height.    
   
   
       16 . The semiconductor device of  claim 15 , wherein the cell gate structures each include: 
 a tunneling dielectric pattern;    a charge-storage layer disposed on the tunneling dielectric pattern;    an inter-gate dielectric layer disposed on the charge-storage layer; and    a control gate disposed on the inter-gate dielectric layer,    wherein the air gap extends along at least a substantially entire sidewall of the charge-storage layer.    
   
   
       17 . The semiconductor device of  claim 16 , wherein the charge-storage layer comprises a material chosen from nitride, polysilicon, and silicon nano-crystals.  
   
   
       18 . The device of  claim 16 , wherein a top of the cell gate structure is higher than a top of the air gap.  
   
   
       19 . A non-volatile semiconductor memory device comprising: 
 a semiconductor substrate comprising: 
 a cell region; and  
 a peripheral region;  
   a plurality of gate structures formed on the cell region, the plurality of gate structures including: 
 a ground select gate and a string select gate disposed on the cell region, the ground select gate and the string select gate spaced apart from each other; and  
 a plurality of cell gate structures disposed between the ground select gate and the string select gate, wherein each cell gate structure comprises: 
 a tunneling dielectric pattern on the semiconductor substrate;  
 a charge-storage layer disposed on the tunneling dielectric pattern;  
 an inter-gate dielectric layer disposed on the charge-storage layer; and  
 a control gate disposed on the inter-gate dielectric layer;  
 
   a spacer layer pattern disposed on opposing sidewalls of the plurality of gate structures, the spacer layer pattern defining a plurality of air gaps between adjacent gate structures, wherein the air gaps are substantially rectangular in cross-section;    an interlayer insulation layer disposed so as to cover the ground select gate, the string select gate, the plurality of cell gate structures, and the plurality of air gaps; and    a plurality of impurity regions disposed below the air gaps and between the gate structures; and    a bit line overlying the interlayer insulation layer, the bit line coupled to one of the plurality of impurity regions via a bit line contact.    
   
   
       20 . The device of  claim 19 , wherein the spacer layer pattern is formed selectively not to extend along one of the sidewalls of the string select gate adjacent the bit line contact.  
   
   
       21 . The device of  claim 20 , further comprising a common source line disposed adjacent the ground select gate, wherein the spacer layer pattern is formed selectively not to extend along one of the sidewalls of the ground select gate facing the common source line.  
   
   
       22 . The device of  claim 19 , wherein the spacer layer pattern comprises an upper portion and a lower portion, the lower portion having a substantially uniform thickness along substantially the entire sidewalls of the gate structures.  
   
   
       23 . The device of  claim 22 , wherein the upper portion of the spacer layer pattern overhangs the tops of the air gaps and the interlayer insulation layer covers the remaining portion of the tops of the air gaps.  
   
   
       24 . A method comprising: 
 forming at least two adjacent gate structures on a semiconductor substrate;    forming a first insulation layer pattern covering a portion of opposing sidewalls of the at least two adjacent gate structures, the first insulation layer pattern extending between the at least two adjacent gate structures;    forming a second insulation layer pattern over a portion of the first insulation layer pattern between the at least two adjacent gate structures, wherein the second insulation layer pattern having an opening to expose a top surface of the first insulation layer pattern; and    removing the first insulation layer pattern, thereby forming an air gap between the at least two adjacent gate structures.    
   
   
       25 . The method of  claim 24 , wherein forming a first insulation layer pattern comprises: 
 forming a first insulation layer covering the top and the sidewalls of the gate structures; and    etching a portion of the first insulation layer so as to expose the portion of the sidewalls of the gate structures.    
   
   
       26 . The method of  claim 24 , wherein the gate structure comprises a charge-storage layer, an inter-gate dielectric layer, and a control gate, the first insulation layer having an etch selectivity with respect to the inter-gate dielectric layer.  
   
   
       27 . The method of  claim 24 , wherein forming a second insulation layer pattern comprises: 
 forming a second insulation layer over the first insulation layer pattern; and    partially etching the second insulation layer to expose the top surface of the first insulation layer.    
   
   
       28 . The method of  claim 24 , which further comprises forming a protection layer on a top and the sidewalls of the at least two adjacent gate structures before forming the first insulation layer pattern.  
   
   
       29 . The method of  claim 28 , wherein the protection layer has an etch selectivity with respect to the first insulation layer pattern.  
   
   
       30 . The method of  claim 24 , which further comprises forming an interlayer insulation layer directly overlying the air gap.  
   
   
       31 . A method of manufacturing a semiconductor device comprising: 
 forming at least two adjacent cell gate structures on a semiconductor substrate;    forming a protection layer covering a top and sidewalls of the at least two cell gate structures;    forming a first insulation layer overlying the protection layer;    etching a portion of the first insulation layer to form the first insulation layer pattern that exposes a portion of the sidewalls of the gate structures;    forming a second insulation layer over the first insulation layer and the exposed sidewalls of the gate structures;    etching a portion of the second insulation layer to form a second insulation layer pattern having an opening that exposes an upper surface of the first insulation layer; and    removing the first insulation layer pattern, using the second insulation layer pattern and the protection layer as a mask, thereby forming an air gap between the sidewalls of the at least two adjacent gate structures.    
   
   
       32 . The method of  claim 31 , wherein the air gap is substantially rectangular in cross-section.  
   
   
       33 . The method of  claim 31 , wherein each gate structure comprises a tunneling dielectric layer, a charge-storage layer, an inter-gate dielectric layer, and a control gate, which are sequentially formed on the semiconductor substrate, the air gap extending along substantially the entire sidewalls of the charge-storage layer.  
   
   
       34 . The method of  claim 31 , wherein the first insulation layer has an etch selectivity with respect to both the protection layer and the second insulation layer pattern.  
   
   
       35 . The method of  claim 31 , wherein the first insulation layer comprises silicon oxide, and wherein the protection layer and the second insulation layer pattern each comprise silicon nitride such that the air gap is substantially surrounded by the protection layer and the second insulation layer pattern.  
   
   
       36 . The method of  claim 31 , wherein removing the first insulation layer pattern comprises a wet etching process.  
   
   
       37 . The method of  claim 36 , wherein the wet etching process comprises hydrofluoric acid.  
   
   
       38 . A method of manufacturing a semiconductor memory device, the method comprising: 
 forming a tunneling dielectric pattern on a semiconductor substrate having a cell region and a peripheral region;    forming a plurality of gate structures formed on the cell region, the plurality of gate structures including: 
 a ground select gate and a string select gate disposed on the cell region, the ground select gate and the string select gate spaced apart from each other; and  
 a plurality of cell gate structures disposed between the ground select gate and the string select gate, wherein each cell gate structure comprises: 
 a tunneling dielectric pattern on the semiconductor substrate;  
 a charge-storage layer disposed on the tunneling dielectric pattern;  
 an inter-gate dielectric layer disposed on the charge-storage layer; and  
 a control gate disposed on the inter-gate dielectric layer;  
 
   forming spacer layer patterns on opposing sidewalls of the plurality of gate structures, the spacer layer patterns defining a plurality of air gaps between adjacent gate structures, wherein the air gaps are substantially rectangular in cross-section;    forming an interlayer insulation layer to cover the ground select gate, the string select gate, the plurality of cell gate structures, and the plurality of air gaps; and    forming a bit line coupled to one of the plurality of impurity regions via a bit line contact adjacent the string select gate where one of the spacer layer patterns is removed.    
   
   
       39 . The method of  claim 38 , which further comprises selectively removing one of the spacer layer patterns from one sidewall of the string select gate opposite another sidewall facing the cell gate structure;  
   
   
       40 . The method of  claim 39 , wherein selectively removing comprises using a wet etching process or dry etching.  
   
   
       41 . The method of  claim 40 , wherein the wet etching uses a phosphoric acid.  
   
   
       42 . The method of  claim 39 , which further comprises: 
 forming a common source line adjacent the ground select gate; and    selectively removing one of the spacer layer patterns from one sidewall of the ground select gate opposite another sidewall facing the common source line;    
   
   
       43 . A system comprising: 
 a dynamic random access memory (DRAM) device; and    a non-volatile memory device, the non-volatile memory device comprising: 
 a plurality of cell gate structures; and  
 an air gap disposed between adjacent cell gate structures in the plurality of cell gate structures, wherein the air gap is substantially rectangular in cross-section.  
   
   
   
       44 . The system of  claim 43 , further comprising a microprocessor operatively coupled to the DRAM device and the non-volatile memory device.  
   
   
       45 . The system of  claim 43 , wherein the DRAM device and the non-volatile memory device are disposed in a single integrated circuit (IC) package.  
   
   
       46 . The system of  claim 43 , wherein the air gap has a substantially uniform width over its height.