Bipolar transistor and method for fabricating the same

Abstract

A bipolar transistor includes: a first semiconductor layer having an intrinsic base region and an extrinsic base region; and a second semiconductor layer having a portion located on the intrinsic base region to be an emitter region or a collector region. A capacitive film is provided on the extrinsic base region using the same semiconductor material as that for the second semiconductor layer. A base electrode is formed on the first semiconductor layer to cover the capacitive film and the extrinsic base region.

1 - 11 . (canceled)  
   
   
       12 . A method for fabricating a bipolar transistor, the method comprising the steps of: 
 a) forming a first semiconductor layer and a second semiconductor layer in this order over a substrate;    b) defining, in the second semiconductor layer, a first region to be an emitter region or a collector region and a second region to be a capacitive film; and    c) forming a base electrode on the first semiconductor layer such that part of the base electrode is connected to the first semiconductor layer and the other part of the base electrode covers the second region.    
   
   
       13 . The method of  claim 12 , wherein the step b) includes the steps of: 
 forming a mask pattern covering the first region and the second region; and    etching the second semiconductor layer using the mask pattern until the first semiconductor layer is exposed.    
   
   
       14 . The method of  claim 13 , wherein in the step b), the mask pattern is formed such that the first region and the second region are in contact with each other.  
   
   
       15 . The method of  claim 13 , including the step of performing ion implantation on the exposed surface of the first semiconductor layer using the mask pattern, after the step b) has been performed.  
   
   
       16 . The method of  claim 13 , wherein in the step c), the base electrode is formed to cover the exposed surface of the first semiconductor layer and the second region of the second semiconductor layer.  
   
   
       17 . The method of  claim 12 , wherein the step c) includes the steps of: 
 forming a first base electrode to be connected to the first semiconductor layer; and    forming a second base electrode on the second semiconductor layer.    
   
   
       18 . The method of  claim 17 , wherein a metallic material whose resistance value increases as the temperature rises is used as a material constituting the second base electrode.  
   
   
       19 . The method of  claim 17 , wherein the step b) includes the steps of: 
 forming a mask pattern covering the first region and the second region; and    etching the second semiconductor layer using the mask pattern until the first semiconductor layer is exposed,    wherein in the step c), the first base electrode is formed on the second region of the second semiconductor layer, and the second base electrode is formed on the exposed surface of the first semiconductor layer.    
   
   
       20 . The method of  claim 17 , wherein in the step b), the second region is defined to cover an end of the first semiconductor layer, and 
 the step c) includes the steps of:    forming a first base electrode on the second region using a first metallic material;    forming a second base electrode on the second region using a second metallic material such that the second base electrode is located at a larger distance from the first region than the first base electrode; and    selectively diffusing the second metallic material so that the second base electrode and the first semiconductor layer are connected to each other.    
   
   
       21 . The method of  claim 12 , wherein in the step a), a material exhibiting a band gap wider than the first semiconductor layer is used as a material constituting the second semiconductor layer.