Mos transistor with recessed gate and method of fabricating the same

Abstract

A MOS transistor with a recessed gate and a method of fabricating the same: The MOS transistor comprises a semiconductor substrate, and a trench isolation layer located in a predetermined region of the semiconductor substrate for defining an active region. The trench isolation layer has a negative slope on at least a lower sidewall thereof. A recessed gate is located in a predetermined region of the active region, and a bottom surface of the recessed gate is placed adjacent the negatively slopped sidewall of the trench isolation layer.

1 . A method of fabricating a MOS transistor comprising: 
 a) preparing a semiconductor substrate;    b) forming an isolation trench having a negative slope on at least a lower sidewall in the semiconductor substrate to define an active region therein;    c) filling the isolation trench with an insulating layer;    d) planarizing the semiconductor substrate having the isolation trench filled with the insulating layer so as to form a trench isolation layer; and    e) forming a recessed gate in the active region, a bottom surface of the recessed gate adjacent the negatively slopped lower sidewall of the trench isolation layer.    
   
   
       2 . The method of fabricating a MOS transistor according to  claim 1 , wherein forming the isolation trench is performed such that the isolation trench has a negative slope on the overall sidewall including the lower sidewall.  
   
   
       3 . The method of fabricating a MOS transistor according to  claim 1 , wherein forming the isolation trench is performed such that the isolation trench has a positive slope on an upper sidewall and a negative slope on the lower sidewall.  
   
   
       4 . The method of fabricating a MOS transistor according to  claim 1 , wherein forming the isolation trench is performed by using a negative-slope etching such that the sidewall has a negative slope.  
   
   
       5 . The method of fabricating a MOS transistor according to  claim 4 , wherein the negative-slope etching is performed using a dry etching or wet etching process.  
   
   
       6 . The method of fabricating a MOS transistor according to  claim 5 , wherein the dry etching is performed using a etching gas including NF 3  and SF 6 .  
   
   
       7 . The method of fabricating a MOS transistor according to  claim 1 , further comprising forming a liner inside the isolation trench, before filling the isolation trench with the insulating layer.  
   
   
       8 . The method of fabricating a MOS transistor according to  claim 1 , wherein filling the isolation trench with the insulating layer comprises: 
 i) partially filling the isolation trench with a first insulating layer;    ii) etching anisotropically the first insulating layer to form an insulating spacer on at least a portion of the negatively slopped lower sidewall of the isolation trench; and    iii) filling the isolation trench having the insulating spacer therein with a second insulating layer.    
   
   
       9 . The method of fabricating a MOS transistor according to  claim 8 , wherein the first insulating layer is formed of HDP-CVD insulating layer.  
   
   
       10 . The method of fabricating a MOS transistor according to  claim 8 , wherein the second insulating layer is formed of HDP-CVD insulating layer.  
   
   
       11 . The method of fabricating a MOS transistor according to  claim 8 , wherein the step of etching anisotropically the first insulating layer is performed using a RIE process.  
   
   
       12 . The method of fabricating a MOS transistor according to  claim 8 , wherein the insulating spacer is formed to cover at least a portion of the negatively slopped lower sidewall.  
   
   
       13 . The method of fabricating a MOS transistor according to  claim 1 , wherein forming the recessed gate comprises: 
 i) forming a channel trench in a predetermined region of the active region such that a bottom surface of the channel trench is placed adjacent a negatively slopped lower sidewall of the trench isolation layer;    ii) forming a gate insulating layer on the bottom surface of the channel trench;    iii) forming a gate conductive layer on the gate insulating layer to fill the channel trench; and    iv) patterning the gate conductive layer.    
   
   
       14 . The method of fabricating a MOS transistor according to  claim 13 , further comprising performing a channel ion implantation process onto the channel trench before forming the gate insulating layer.  
   
   
       15 . The method of fabricating a MOS transistor according to  claim 13 , wherein the gate conductive layer is formed of polysilicon.