US2007090446A1PendingUtilityA1
Hardmask etch for gate polyetch
Est. expiryMay 30, 2022(expired)· nominal 20-yr term from priority
Inventors:Koji Tamura
H10D 64/01306H10P 50/283H10P 50/268H10P 50/71Y10S438/952
47
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Claims
Abstract
A semiconductor device is provided that comprises a substrate; an oxide layer over the substrate; and a silicon layer over the oxide layer, the silicon layer forming a notch-free gate structure; wherein the gate structure has been formed using a hard mask comprising an antireflective layer over a silicon oxide layer, the mask having been subsequently removed.
Claims
exact text as granted — not AI-modified1 . A semiconductor device that comprises:
a substrate; an oxide layer over the substrate; and a silicon layer over the oxide layer, the silicon layer forming a notch-free gate structure; wherein the gate structure has been formed using a hard mask comprising an antireflective layer over a silicon oxide layer, the mask having been subsequently removed.
2 . The semiconductor device of claim 1 , wherein the antireflective layer comprises silicon oxynitride.
3 . The semiconductor device of claim 1 , wherein the silicon oxide layer has a thickness of about 300-700 Å.
4 . The semiconductor device of claim 1 , wherein the antireflective coating has a thickness of about 300-700 Å.
5 . The semiconductor device of claim 1 , wherein the silicon layer comprises non-doped or n-doped poly-Si.
6 . The semiconductor device of claim 1 , wherein the silicon layer has a thickness of about 2000 Å.Join the waitlist — get patent alerts
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