Mos transistor with recessed gate and method of fabricating the same

Abstract

A MOS transistor with a recessed gate and a method of fabricating the same: The MOS transistor comprises a semiconductor substrate, and a trench isolation layer located in a predetermined region of the semiconductor substrate for defining an active region. The trench isolation layer has a negative slope on at least a lower sidewall thereof. A recessed gate is located in a predetermined region of the active region, and a bottom surface of the recessed gate is placed adjacent the negatively slopped sidewall of the trench isolation layer.

1 . A MOS transistor comprising: 
 a semiconductor substrate;    a trench isolation layer located in the semiconductor substrate for defining an active region, wherein the trench isolation layer has a positive slope on an upper sidewall and a negative slope on the lower sidewall; and    a recessed gate located in the active region, a bottom surface of the recessed gate placed adjacent the negatively slopped sidewall of the trench isolation layer.    
   
   
       2 . The MOS transistor according to  claim 1 , wherein the trench isolation layer is formed of HDP-CVD insulating layer.  
   
   
       3 . The MOS transistor according to  claim 1 , further comprising a gate insulating layer interposed between the recessed gate and the active region.  
   
   
       4 . The MOS transistor according to  claim 1 , wherein the recessed gate is formed of polysilicon.