Freeway routing system for a gate array

Abstract

A freeway routing system for connecting input and output ports of interface groups of tiles in a field programmable gate array. The freeway system has a first set of routing conductors configured to transfer signals between the input ports of interface groups in a first tile of the field programmable gate array and the output ports of interface groups of other tiles in the field programmable gate array. The first set conductors include vertical conductors that form intersections with horizontal conductors and programmable interconnect elements located at the intersections of the vertical conductors and horizontal conductors in a diagonal orientation to connect each of the horizontal conductors to one of the vertical conductors.

1 . A method of routing the internal components in a FPGA tile comprising: 
 inputting a function netlist defining a user circuit;    optimizing said user circuit;    placing user cells defining said user circuit into said FPGA internal components;    using a first set of routing conductors to route said user circuit to interconnect said internal components to implement said user circuit; and    engaging a freeway set of routing conductors to meet said user circuit routing requirements;    generating a programming bitstream defining said user circuit; and    programming said FPGA functional unit with said bitstream to implement said user circuit.    
   
   
       2 . A method of routing the internal components in a FPGA tile comprising: 
 inputting a function netlist defining a user circuit;    optimizing said user circuit;    placing user cells defining said user circuit into said FPGA internal components;    using a first set of routing conductors and a freeway set of routing conductors to route said user circuit to interconnect said internal components to implement said user circuit;    generating a programming bitstream defining said user circuit; and    programming said FPGA functional unit with said bitstream to implement said user circuit.    
   
   
       3 . A method of providing a freeway interconnect structure in a FPGA comprising: 
 providing a plurality of FPGA tiles;    providing a plurality of functional groups (FGs) arranged in rows and columns on each said FPGA tile;    providing a plurality of interface groups (IGs) surrounding said plurality of FGs such that one IG is positioned at each end of each row and column, each of the IGs having a first, second and third set of input ports and a first, second and third set of output ports;    providing a freeway set of routing conductors configured to transfer signals to said first, second and third input ports of IGs of one FPGA tile, and configured to transfer signals from said first, second and third output ports of IGs of all other FPGA tiles;    said act of providing a freeway set of routing conductors comprising: 
 providing a plurality of vertical conductors that form intersections with a plurality of horizontal conductors; and  
 providing programmable interconnect elements located at said intersections in a diagonal orientation on said FPGA tile.  
   
   
   
       4 . The method of  claim 3  further comprising: 
 providing at least one other FPGA tile configured in the same manner as said first FPGA; and    connecting said freeway set of routing conductors of each FPGA tile to any adjacent FPGA tile's freeway set of routing conductors.    
   
   
       5 . The method of  claim 4 , further comprising: 
 providing programmable interconnect elements located at said connections between adjacent FPGA tiles.    
   
   
       6 . The method of  claim 3 , further comprising configuring said freeway set of routing conductors to also transfer signals from output ports of at least one IO.  
   
   
       7 . The method of  claim 3 , further comprising configuring said freeway set of routing conductors to also transfer signals from output ports of at least one RAM.  
   
   
       8 . An apparatus for routing the internal components in a FPGA tile comprising: 
 means for inputting a function netlist defining a user circuit;    means for optimizing said user circuit;    means for placing user cells defining said user circuit into said FPGA internal components;    means for using a first set of routing conductors to route said user circuit to interconnect said internal components to implement said user circuit;    means for determining whether the routing requirements of said user circuit have been met using said first set of routing conductors;    means for engaging a freeway set of routing conductors to meet said user circuit routing requirements;    means for generating a programming bitstream defining said user circuit; and    means for programming said FPGA functional unit with said bitstream to implement said user circuit.    
   
   
       9 . An apparatus for routing the internal components in a FPGA tile comprising: 
 means for inputting a function netlist defining a user circuit;    means for optimizing said user circuit;    means for placing user cells defining said user circuit into said FPGA internal components;    means for using a first set of routing conductors and a freeway set of routing conductors to route said user circuit to interconnect said internal components to implement said user circuit;    means for generating a programming bitstream defining said user circuit; and    means for programming said FPGA functional unit with said bitstream to implement said user circuit.