Configurable architecture for virtual socket client to an on-chip bus interface block

Abstract

An interface block provides an interface between an internal bus of an integrated circuit and a socket of a logic block. The interface block includes a synchronization module that performs any needed synchronization between a clock domain of the internal bus and a clock domain of the socket of the logic block. A translation module provides translation of block encoding of the data for data transferred between the internal bus and the socket of the logic block. A queue module buffers data flowing between the internal bus and the socket of the logic block. A driver module handles low level and electrical drive specifications of the internal bus.

1 .- 12 . (canceled)  
   
   
       13 . An interface block that provides an interface between an internal bus and a socket of a logic block, the interface block comprising: 
 a plurality of modules located on an integrated circuit and connected between the internal bus and the socket of the logic block, wherein each module in the plurality of modules performs only a single function from a plurality of functions including: 
 a first function for providing any needed synchronization between a clock domain of the internal bus and a clock domain of the socket of the logic block,  
 a second function for providing any required translation of block encoding of data transferred between the internal bus and the socket of the logic block,  
 a third function for providing any buffering of data flowing between the internal bus and the socket of the logic block, and  
 a fourth function for providing a handling of any low level and electrical drive specifications of the internal bus.  
   
   
   
       14 . The interface block of  claim 13 , wherein one of the plurality of modules is a synchronization module that performs the first function.  
   
   
       15 . The interface block of  claim 13 , wherein one of the plurality of modules is a translation module that performs the second function.  
   
   
       16 . The interface block of  claim 13 , wherein one of the plurality of modules is a queue module that performs the third function.  
   
   
       17 . The interface block of  claim 13 , wherein one of the plurality of modules is a driver module that performs the fourth function.  
   
   
       18 . The interface block of  claim 13 , wherein one of the plurality of modules is a synchronization module that exclusively performs the first function.  
   
   
       19 . The interface block of  claim 13 , wherein one of the plurality of modules is a translation module that exclusively performs the second function.  
   
   
       20 . The interface block of  claim 13 , wherein one of the plurality of modules is a queue module that exclusively performs the third function.  
   
   
       21 . The interface block of  claim 13 , wherein one of the plurality of modules is a driver module that exclusively performs the fourth function.  
   
   
       22 . The interface block of  claim 13 , further comprising: 
 a plurality of buffers, each buffer situated between a pair of modules in the plurality of modules, the plurality of buffers used to pipeline the interface block.    
   
   
       23 . An interface block that provides an interface between an internal bus and a socket of a logic block, the interface block comprising: 
 a plurality of modules located on an integrated circuit, wherein each module in the plurality of modules exclusively performs only a single function from a plurality of functions including: 
 a first function for providing any needed synchronization between a clock domain of the internal bus and a clock domain of the socket of the logic block,  
 a second function for providing any required translation of block encoding of data transferred between the internal bus and the socket of the logic block,  
 a third function for providing any buffering of data flowing between the internal bus and the socket of the logic block, and  
 a fourth function for providing a handling of any low level and electrical drive specifications of the internal bus.  
   
   
   
       24 . The interface block of  claim 23 , wherein one of the plurality of modules is a synchronization module that exclusively performs the first function.  
   
   
       25 . The interface block of  claim 23 , wherein one of the plurality of modules is a translation module that exclusively performs the second function.  
   
   
       26 . The interface block of  claim 23 , wherein one of the plurality of modules is a queue module that exclusively performs the third function.  
   
   
       27 . The interface block of  claim 23 , wherein one of the plurality of modules is a driver module that exclusively performs the fourth function.  
   
   
       28 . The interface block of  claim 23 , further comprising: 
 a plurality of buffers, each buffer situated between a pair of modules in the plurality of modules, the plurality of buffers used to pipeline the interface block.