Nitride read only memory device with buried diffusion spacers and method for making the same

Abstract

A method for making a nitride read only memory device with buried diffusion spacers is disclosed. An oxide-nitride-oxide (ONO) layer is formed on top of a silicon substrate, and a polysilicon gate is formed over the ONO layer. The polysilicon gate is formed less than a length of the ONO layer. Two buried diffusion spacers are formed beside two sidewalls of the polysilicon gate and over the ONO layer. Two buried diffusion regions are implanted on the silicon substrate next to the two buried diffusion spacers. The two buried diffusion regions are then annealed such that the approximate interfaces of the buried diffusion regions are under the sidewalls of the polysilicon gate. The structure of a nitride read only memory device with buried diffusion spacers is also described.

1 . A memory device, comprising: 
 a silicon substrate having first and second buried diffusion regions;    an oxide-nitride-oxide (ONO) layer defined over the silicon substrate;    a polysilicon gate defined over potion of the ONO layer between the first and second buried diffusion regions, the polysilicon gate having a first side and a second side, the polysilicon gate extending a length between the first and second buried diffusion regions such that each of the first side and the second side of the polysilicon gate is above an approximate interface of the first and second buried diffusion regions; and    first and second insulator spacers positioned respectively beside the first side and the second side of the polysilicon gate.    
   
   
       2 . The memory device as recited in  claim 1 , further comprising: 
 first and second oxide regions positioned respectively beside the first and second insulator spacers.    
   
   
       3 . The memory device as recited in  claim 2 , further comprising: 
 a polysilicon layer defined over the polysilicon gate, the first and second insulator spacers, and the first and second oxide regions.    
   
   
       4 . The memory device as recited in  claim 3 , wherein the polysilicon layer defines as a word line.  
   
   
       5 . The memory device as recited in  claim 1 , wherein each of the first and second insulator spacers is made of oxide.  
   
   
       6 . The memory device as recited in  claim 1 , wherein each of the first and second insulator spacers has a thickness of between about 100 angstroms to about 500 angstroms.  
   
   
       7 . The memory device as recited in  claim 1 , wherein the first and second buried diffusion regions are define as bit lines.  
   
   
       8 . A method for making a memory device, comprising: 
 providing a silicon substrate;    forming an oxide-nitride-oxide (ONO) layer on top of the silicon substrate;    forming a polysilicon gate over the ONO layer;    forming first and second insulator spacers beside a first side and a second side of the polysilicon gate;    implanting first and second buried diffusion regions on the silicon substrate respectively next to and between the first and second insulator spacers; and    annealing the first and second buried diffusion regions such that approximate interfaces of the first and second buried diffusion regions are defined, each of the approximate interfaces of the first and second buried diffusion regions being respectively under the first side and the second side of the polysilicon gate.    
   
   
       9 . The method for making a memory device as recited in  claim 8 , further comprising: 
 forming first and second oxide regions respectively beside and between the first and second insulator spacers.    
   
   
       10 . The method for making a memory device as recited in  claim 9 , further comprising: 
 depositing a polysilicon layer over the first and second oxide regions, the first and second insulator spacers, and the polysilicon gate.    
   
   
       11 . The method for making a memory device as recited in  claim 8 , wherein forming the first and second insulator spacers is performed by depositing a conformal insulator layer over the polysilicon gate and then etching off portion of the conformal insulator layer on top of the polysilicon gate.  
   
   
       12 . The method for making a memory device as recited in  claim 8 , wherein implanting the first and second buried diffusion regions is performed by a buried diffusion implantation process and a pocket implantation process.  
   
   
       13 . The method for making a memory device as recited in  claim 8 , wherein annealing the first and second buried diffusion regions is performed by a rapid thermal anneal process.  
   
   
       14 . The method for making a memory device as recited in  claim 8 , wherein forming the polysilicon gate is performed by depositing a polysilicon layer on the top of the silicon substrate, patterning the polysilicon layer with photoresist, and etching portions of the polysilicon layer which is not covered by the photoresist until the ONO layer is exposed.  
   
   
       15 . The method for making a memory device as recited in  claim 8 , wherein each of the first and second insulator spacers is defined by a type of oxide.  
   
   
       16 . The method for making a memory device as recited in  claim 8 , wherein making the memory device can be integrated with making a periphery device by dividing the silicon substrate into a memory region and a periphery region and making the memory device and the periphery device respectively over the memory region and the periphery region on the silicon substrate.  
   
   
       17 . The method for making a memory device as recited in  claim 16 , wherein the ONO layer of the memory device is formed by depositing a layer of ONO over the top of the silicon substrate covering both the memory region and the periphery region and patterned etching off a portion of the layer of ONO belonging to the periphery region to prepare for a periphery gate oxide deposition.  
   
   
       18 . The method for making a memory device as recited in  claim 17 , wherein the periphery gate oxide deposition is performed by depositing a periphery gate oxide layer over the silicon substrate belonging to the peripheral region.  
   
   
       19 . The method for making a memory device as recited in  claim 18 , wherein making the periphery device is performed by forming a periphery polysilicon gate over the periphery gate oxide layer and forming first and second periphery insulator spacers beside a first side and a second side of the periphery polysilicon gate.  
   
   
       20 . The method for making a memory device as recited in  claim 16 , wherein the memory device and the periphery device is separated by interlayer dielectric.