Compression of Emulation Trace Data

Abstract

A system and method for compressing trace data from an emulation system. Scan chains may receive trace data from configurable logic blocks inside one or more emulation chips, and the data received from the scan chains may be compressed. Where delta compression is used, the scan chains may also perform a delta detection function. Alternatively, delta detection may be performed using the outputs of the scan chains. In addition, event detectors may be implemented within or outside of the scan chains. Compression of the trace data may include receiving a plurality of data sets and performing compression along cross-sections of the combined data sets.

1 . In an emulation system, an integrated circuit chip including a scan chain disposed therein, the scan chain configured to receive a set of first data representing states of a plurality of configurable logic blocks of the integrated circuit chip at a first time and a set of second data representing states of the plurality of configurable logic blocks at a second time, the scan chain further configured to output a set of second data representing whether a delta has occurred between the first set of data and the second set of data.  
   
   
       2 . The integrated circuit chip of  claim 1 , wherein the integrated circuit chip is an application-specific integrated circuit (ASIC).  
   
   
       3 . The integrated circuit chip of  claim 1 , wherein the integrated circuit chip includes reconfigurable logic.  
   
   
       4 . The integrated circuit chip of  claim 1 , wherein the scan chain includes an XOR gate having a first input coupled to an input of a flip-flop and a second input coupled to an output of the flip-flop.  
   
   
       5 . The integrated circuit chip of  claim 4 , wherein the scan chain includes a multiplexor having a first input coupled to an output of the XOR gate and a second input coupled to the input of the flip-flop.  
   
   
       6 . The integrated circuit chip of  claim 1 , wherein the scan chain receives a clock and is further configured to intermittently output data representing states of at least some of the plurality of configurable logic blocks on fewer than all clock cycles.  
   
   
       7 . An emulation system comprising: 
 a plurality of integrated circuit chips, each integrated circuit chip including reconfigurable logic, each chip outputting compressed emulation trace data; and    a storage device configured to store the compressed emulation trace data from the integrated circuit chips.    
   
   
       8 . The emulation system of  claim 7 , wherein each of the integrated circuit chips is an application-specific integrated circuit (ASIC).  
   
   
       9 . The emulation system of  claim 7 , wherein each of the integrated circuit chips further includes a compression circuit configured to generate the compressed emulation trace data and a first-in-first-out buffer configured to transfer the compressed emulation trace data out of the integrated circuit chip at no more than a predetermined maximum bandwidth.  
   
   
       10 . An emulation system comprising: 
 means for emulating a circuit design;    means for obtaining emulation trace data in connection with the circuit design during emulation; and    means for compressing the emulation trace data.    
   
   
       11 . The emulation system of  claim 10 , further including means for storing the compressed emulation trace data.  
   
   
       12 . An emulation system in communication with a workstation via a communication channel, the workstation being on one side of the communication channel, the emulation system comprising: 
 an emulator configured to generate trace data; and    a trace compressor coupled to the emulation resource and configured to compress the trace data,    wherein both the emulator and the trace compressor are on the other side of the communication channel.    
   
   
       13 . The emulation system of  claim 12 , wherein the emulator and the trace compressor are both disposed in a same integrated circuit chip.  
   
   
       14 . The emulation system of  claim 12 , wherein the emulator comprises a first integrated circuit chip and the compressor comprises a second different integrated circuit chip.  
   
   
       15 . An emulation system comprising: 
 a housing;    an emulator disposed within the housing and configured to generate trace data; and    a trace compressor disposed within the housing, coupled to the emulator, and configured to compress the trace data.