US2007077724A1PendingUtilityA1

Etching methods and apparatus and substrate assemblies produced therewith

Assignee: MICRON TECHNOLOGY INCPriority: Jun 29, 1999Filed: Aug 31, 2006Published: Apr 5, 2007
Est. expiryJun 29, 2019(expired)· nominal 20-yr term from priority
H10P 50/694H10P 50/283H10P 50/268H10P 50/73H10P 50/71H10W 10/0145H10W 10/17Y10T428/24479H01J 2237/3347Y10S428/901H01J 2237/3345H01J 37/321Y10T428/2457
51
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

Methods and apparatus for etching substrates such as silicon wafers are provided. In one specific approach, a surface of the substrate assembly is covered with a resist that is patterned to define features to be etched. In this approach, the surface is then exposed to a plasma in a plasma etcher so that surface areas not covered with the resist are etched, while the thickness of the resist increases or etches at a rate that is at least ten times slower than that of the exposed areas of the surface. This etching process can be followed with a conventional plasma etch. By combining the etching that increases the resist thickness with the conventional etching of resist in which the resist thins during etching, features having high-aspect-ratios can be etched.

Claims

exact text as granted — not AI-modified
1 .- 46 . (canceled)  
   
   
       47 . A method of etching a high-aspect-ratio feature having a controlled profile, comprising: 
 selecting a surface of a substrate assembly to be etched;    selecting a depth D and width d of the high-aspect-ratio feature such that D/d>10;    forming a resist layer of thickness less than about D/5 on the selected surface of the substrate assembly; and    etching the high-aspect-ratio feature into the selected surface with a controlled profile.    
   
   
       48 . The method of  claim 47 , wherein the substrate assembly comprises a silicon wafer.  
   
   
       49 . The method of  claim 47 , wherein the substrate assembly comprises a silicon wafer having a layer of silicon oxide on the selected surface.  
   
   
       50 . The method of  claim 47 , wherein the thickness of the resist layer is selected to be less than about D/7.5.  
   
   
       51 . The method of  claim 47 , wherein the thickness of the resist layer is selected to be less than about D/10.  
   
   
       52 . The method of  claim 47 , wherein the thickness of the resist layer is selected to be less than about D/15.  
   
   
       53 . A method of etching a high-aspect-ratio feature having a controlled profile, comprising: 
 forming a layer of insulating material above a semiconducting substrate;    selecting a surface of the layer of insulating material to be etched;    selecting a depth D and width d of the high-aspect-ratio feature such that D/d>10;    forming a resist layer of thickness less than about D/5 on the selected surface of the layer of insulating material; and    etching the high-aspect-ratio feature into the selected surface of the layer of insulating material with a controlled profile.    
   
   
       54 . The method of  claim 53 , wherein the semiconducting substrate comprises a silicon wafer.  
   
   
       55 . The method of  claim 53 , wherein the thickness of the resist layer is selected to be less than about D/7.5.  
   
   
       56 . The method of  claim 53 , wherein the thickness of the resist layer is selected to be less than about D/10.  
   
   
       57 . The method of  claim 53 , wherein the thickness of the resist layer is selected to be less than about D/15.

Join the waitlist — get patent alerts

Track US2007077724A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.