Trench memory cell and method for making the same

Abstract

A process is provided for forming a trench capacitor, such as used in a DRAM memory cell, in which the required number of polysilicon deposition steps and planarization steps are reduced. A first region of a first material is formed in the bottom portion of the trench, and a dielectric material for the collar structure is subsequently formed above this region on a portion of the trench sidewalls. A removable material, such as a resist or spin-on glass, is then provided in the trench, overlying the first material and in contact with the lower portion of the collar dielectric material. The upper portion of the collar structure is then removed, after which the removable material is removed to again expose the upper surface of the first region. A second region of a second material, overlying and in contact with the first region, is then formed; the second region has an upper surface below the surface of the substrate. The first and second materials are conducting materials, typically polysilicon. The capacitor thus may be formed with only two polysilicon deposition processes; the interface between the first and second materials is the only interface between conducting materials in the trench.

1 - 22 . (canceled)  
   
   
       23 . A capacitor structure in a trench formed in a substrate, the capacitor structure comprising: 
 a first region in a bottom portion of the trench, the first region including 
 a dielectric layer on a bottom of the trench and on a lower portion of sidewalls of the trench, and  
 a first conducting material;  
   a collar structure of a dielectric material disposed on the sidewalls of the trench above the first region; and    a second region including a second conducting material in contact with the first conducting material at an interface between the first region and the second region, the second region extending above the collar structure.    
   
   
       24 . A capacitor structure according to  claim 23 , wherein the first material and the second material are each polysilicon.  
   
   
       25 . A capacitor structure according to  claim 23 , wherein the collar structure has a lower end disposed on a previously formed upper surface of the first region, the collar structure thereby being self-aligned to said upper surface.  
   
   
       26 . A capacitor structure according to  claim 23 , wherein an upper portion of the second region is in contact with a conducting region of the substrate at a sidewall of the trench, and said conducting region is electrically connected to a transistor, so that the capacitor and the transistor form a DRAM cell.  
   
   
       27 . A capacitor structure according to  claim 23 , further comprising an isolation region in at least a region of the trench above an upper surface of the second region.  
   
   
       28 . A capacitor structure according to  claim 23 , wherein the interface between the first region and the second region is the only interface between conducting materials in the trench.  
   
   
       29 . A capacitor structure formed in a substrate, the capacitor structure comprising: 
 a first region including a first conducting material in a bottom portion of a trench; and    a second region including an interface with the first region, the second region comprising: 
 a collar structure of a dielectric material disposed along sidewalls of the trench above the first region; and  
 a second conducting material filling within the collar structure and being in contact with the first conducting material at the interface, wherein the second conducting material extending above and covering the collar structure.  
   
   
   
       30 . A capacitor structure according to  claim 29 , wherein at least one of the first conducting material and the second conducting material comprises polysilicon.  
   
   
       31 . A capacitor structure according to  claim 29 , wherein the collar structure has a lower end disposed along an upper surface of a dielectric layer of the first region, the dielectric layer being formed along sidewalls of the trench, thereby the collar structure being self-aligned to the upper surface of the dielectric layer.  
   
   
       32 . A capacitor structure according to  claim 29 , wherein an upper portion of the second region is in contact with a conducting region of the substrate at at least a portion of a sidewall of the trench, and said conducting region is electrically connected to a transistor, so that the capacitor and the transistor form a DRAM cell.  
   
   
       33 . A capacitor structure according to  claim 29 , further comprising an isolation region in at least a region of the trench above an upper surface of the second region.  
   
   
       34 . A capacitor structure according to  claim 29 , wherein the interface between the first region and the second region is the only interface between conducting materials in the trench.  
   
   
       35 . A dynamic random access memory (DRAM) cell, comprising: 
 a transistor formed in a substrate; and    a capacitor structure being electrically connected to the transistor, the capacitor structure comprising: 
 a first region including a first conducting material in a bottom portion of a trench; and  
 a second region including an interface with the first region, the second region comprising: 
 a collar structure of a dielectric material disposed along sidewalls of the trench above the first region; and  
 a second conducting material filling within the collar structure and being in contact with the first conducting material at the interface, wherein the second conducting material extending above and covering the collar structure.  
 
   
   
   
       36 . A DRAM cell according to  claim 35 , wherein one or more of the first and the second conducting materials comprise polysilicon.  
   
   
       37 . A DRAM cell according to  claim 35 , wherein the collar structure has a lower end disposed at least partially on top of an upper surface of a dielectric layer of the first region, the dielectric layer being formed along sidewalls of the trench, thereby the collar structure being self-aligned to the upper surface of the dielectric layer.  
   
   
       38 . A DRAM cell according to  claim 35 , wherein the capacitor structure is electrically connected to the transistor through at least a portion of sidewalls of the trench at an upper portion of the second region.  
   
   
       39 . A DRAM cell according to  claim 35 , further comprising an isolation region formed directly on top of an upper surface of the second region inside the trench.  
   
   
       40 . A DRAM cell according to  claim 35 , wherein the interface between the first region and the second region is the only interface between conducting materials in the trench.