Providing a low phase noise reference clock signal

Abstract

A reference clock generator includes an oscillator to generate a periodic signal, a shaping circuit and a filter. The shaping circuit shapes the periodic signal to generate a clock signal. The filter is located between the oscillator and the shaping circuit.

1 . A reference clock generator, comprising: 
 an oscillator to generate a periodic signal;    a shaping circuit to shape the periodic signal to generate a clock signal; and    a filter located between the oscillator and the shaping circuit.    
   
   
       2 . The reference clock generator of  claim 1 , further comprising: 
 a buffer located between the oscillator and the filter.    
   
   
       3 . The reference clock generator of  claim 1 , further comprising: 
 a series regulator coupled to a supply rail to provide power to the oscillator; and    a shunt regulator coupled to the supply rail to provide power to the shaping circuit.    
   
   
       4 . The reference clock generator of  claim 3 , further comprising: 
 a buffer to drive the periodic signal,    wherein the series regulator also provides power to the buffer.    
   
   
       5 . The reference clock generator of  claim 1 , further comprising: 
 a regulator to provide power to the oscillator in response to power received from a supply rail, wherein the regulator has a substantially larger forward power supply rejection ratio to reject noise propagating from the supply rail to the oscillator relative to a reverse power supply rejection ratio of the regulator to reject noise propagating from the oscillator to the supply rail.    
   
   
       6 . The reference clock generator of  claim 5 , wherein the regulator comprises a series regulator.  
   
   
       7 . The reference clock generator of  claim 1 , further comprising: 
 a regulator to provide power to the shaping circuit in response to power received from a supply rail, wherein the regulator has a reverse power supply rejection ratio to reject noise propagating from the shaping circuit to the supply rail which is substantially the same as a forward power supply rejection ratio of the regulator to reject noise propagating from the supply rail to the shaping circuit.    
   
   
       8 . The reference clock generator of  claim 7 , wherein the regulator comprises a shunt regulator.  
   
   
       9 . The reference clock generator of  claim 3 , further comprising: 
 a first regulator to provide power to the oscillator in response to power received from a supply rail, wherein the regulator has a substantially larger forward power supply rejection ratio to reject noise propagating from the supply rail to the oscillator relative to a reverse power supply rejection ratio of the regulator to reject noise propagating from the oscillator to the supply rail; and    a second regulator separate from the first regulator, the second regulator to provide power to the shaping circuit in response to power received from a supply rail, wherein the regulator has a reverse power supply rejection ratio to reject noise propagating from the shaping circuit to the supply rail which is substantially the same as a forward power supply rejection ratio of the regulator to reject noise propagating from the supply rail to the shaping circuit.    
   
   
       10 . A shaping circuit comprising: 
 a first inverter to receive a sinusoidal signal; and    a chain of serially coupled inverters having an input terminal to receive the sinusoidal signal and an output terminal,    wherein the sizes of the inverters progressively increase from the input terminal to the output terminal.    
   
   
       11 . The shaping circuit of  claim 10 , wherein the size of the inverter of the chain closest to the input terminal is smaller than a size of the first inverter.  
   
   
       12 . The shaping circuit of  claim 10 , wherein first inverter and inverters of the chain are complementary metal oxide semiconductor inverters.  
   
   
       13 . The shaping circuit of  claim 10 , wherein first inverter substantially establishes an edge speed of the clock signal.  
   
   
       14 . A frequency synthesizer, comprising: 
 a clock generator to generate a reference clock signal, the clock generator comprising an oscillator having first transistors, each of the first transistors having substantially a first gate oxide thickness; and    a phase locked loop to lock onto the reference clock signal to generate an output signal, the phase locked loop comprising a charge pump having second transistors, each of the second transistors having substantially a second gate oxide thickness substantially greater than the first gate oxide thickness.    
   
   
       15 . The frequency synthesizer of  claim 14 , wherein the phase locked loop further comprises a phase detector having third transistors, each of the third transistors having substantially a third gate oxide thickness substantially smaller than the second gate oxide thickness.  
   
   
       16 . The frequency synthesizer of  claim 14 , wherein the clock generator comprises a shaping circuit to shape a sinusoidal signal provided by the oscillator into the reference clock signal, the shaping circuit having third transistors, each of the third transistors having substantially a third gate oxide thickness substantially smaller than the second gate oxide thickness.  
   
   
       17 . A frequency synthesizer, comprising: 
 a clock generator to generate a reference clock signal, the clock generator comprising an oscillator having first transistors, each of the first transistors having substantially a first gate oxide thickness; and    a phase locked loop to lock onto the reference clock signal to generate an output signal, the phase locked loop comprising a phase detector having second transistors, each of the second transistors having substantially a second gate oxide thickness substantially smaller than the first gate oxide thickness.    
   
   
       18 . The frequency synthesizer of  claim 17 , wherein the phase locked loop further comprises a charge pump having third transistors, each of the third transistors having substantially a third gate oxide thickness substantially greater than the second gate oxide thickness.  
   
   
       19 . The frequency synthesizer of  claim 17 , wherein the clock generator comprises a shaping circuit to shape a sinusoidal signal provided by the oscillator into the reference clock signal, the shaping circuit having third transistors, each of the third transistors having substantially a third gate oxide thickness substantially greater than the second gate oxide thickness.  
   
   
       20 . A method comprising: 
 generating a periodic signal;    shaping the periodic signal to generate a clock signal; and    filtering the periodic signal before the shaping.    
   
   
       21 . The method of  claim 20 , further comprising: 
 providing a buffer to drive the periodic signal.    
   
   
       22 . The method of  claim 20 , further comprising: 
 providing an oscillator to generate the periodic signal; and    providing a regulator to provide power to the oscillator in response to power received from a supply rail, wherein the regulator has a substantially larger forward power supply rejection ratio to reject noise propagating from the supply rail to the oscillator relative to a reverse power supply rejection ratio of the regulator to reject noise propagating from the oscillator to the supply rail.    
   
   
       23 . The method of  claim 22 , wherein the regulator comprises a series regulator.  
   
   
       24 . The method of  claim 20 , further comprising: 
 providing a shaping circuit to perform the act of shaping; and    providing a regulator to power the shaping circuit regulator to provide power to the shaping circuit in response to power received from a supply rail, wherein the regulator has a reverse power supply rejection ratio to reject noise propagating from the shaping circuit to the supply rail which is substantially the same as a forward power supply rejection ratio of the regulator to reject noise propagating from the supply rail to the shaping circuit.    
   
   
       25 . The method of  claim 24 , wherein the regulator comprises a shunt regulator.  
   
   
       26 . A method comprising: 
 providing a chain of serially coupled inverters to convert a sinusoidal signal received and an input terminal of the chain into a clock signal provided at an output terminal of the chain; and    progressively increasing the sizes of the inverters from the input terminal to the output terminal.    
   
   
       27 . The method of  claim 26 , wherein the size of the inverter of the chain closest to the input terminal is smaller than a size of the first inverter.  
   
   
       28 . The method of  claim 26 , wherein first inverter and inverters of the chain are complementary metal oxide semiconductor inverters.  
   
   
       29 . The method of  claim 26 , wherein first inverter substantially establishes an edge speed of the clock signal.  
   
   
       30 . A wireless system comprising: 
 a wireless interface;    a phase locked loop to receive a clock signal; and    a reference clock generator to provide the clock signal to the phase locked loop, the reference clock generator comprising: 
 an oscillator to generate a periodic signal;  
 a shaping circuit to shape the periodic signal to generate a clock signal; and  
 a filter located between the oscillator and the shaping circuit.  
   
   
   
       31 . The wireless system of  claim 30 , further comprising: 
 a buffer located between the oscillator and the filter.    
   
   
       32 . The wireless system of  claim 30 , further comprising: 
 a series regulator coupled to a supply rail to provide power to the oscillator; and    a shunt regulator coupled to the supply rail to provide power to the shaping circuit.