Platinum stuffed with silicon oxide as a diffusion oxygen barrier for semiconductor devices

Abstract

The present invention provides techniques to fabricate high dielectric MIM storage cell capacitors. In one embodiment, this is accomplished by forming a silicon contact is then formed to electrically connect the formed bottom electrode layer in the container with the at least one associated transistor device. A titanium nitride barrier layer is then formed over the silicon contact. An oxygen barrier layer including platinum stuffed with silicon oxide is then formed over the titanium nitride layer and below the bottom electrode layer. A bottom electrode layer is then formed using platinum over interior surfaces of a container formed relative to at lest one associated transistor device on a silicon substrate. Further, a high dielectric insulator layer is formed over the bottom electrode layer. A top electrode layer is then formed over the high dielectric insulator layer.

1 . A computer system, comprising: 
 a computer unit including at least a processor and a memory system in communication with the processor, the memory system including at least one memory device having a memory array including a semiconductor structure having a high dielectric MIM container capacitor and at least one associated transistor device, further comprising:    a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed on a silicon substrate, wherein the bottom electrode comprises platinum;    a high dielectric layer overlying the interior surface of the bottom electrode;    a top electrode overlying the high dielectric layer; and    a polysilicon contact electrically connecting the bottom electrode with the silicon substrate, wherein the polysilicon contact includes a titanium nitride barrier layer overlying the polysilicon contact, and platinum stuffed with silicon oxide barrier layer overlying the titanium nitride layer and underlying the bottom electrode.    
   
   
       2 . The computer system of  claim 1 , wherein the high dielectric insulator layer comprises: 
 a high dielectric insulator layer that is annealed in an oxygen-containing atmosphere to a temperature in the range of about 450° C. to 850° C.    
   
   
       3 . The computer system of  claim 1 , wherein the oxygen barrier layer is about 50 to 5000 Å thick.  
   
   
       4 . The computer system of  claim 1 , wherein the TiN barrier layer is about 50 to 1000 Å thick.  
   
   
       5 . The computer system of  claim 1 , wherein the TiN barrier layer is less than about 150 Å thick.  
   
   
       6 . A computer system, comprising: 
 a computer unit including at least a processor and a memory system in communication with the processor, the memory system including at least one memory device having a memory array including a semiconductor structure having a high dielectric MIM container capacitor and at least one associated transistor device, further comprising:    a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed on a silicon substrate, wherein the bottom electrode comprises rhodium;    a high dielectric layer overlying the interior surface of the bottom electrode;    a top electrode overlying the high dielectric layer; and    a polysilicon contact electrically connecting the bottom electrode with the silicon substrate, wherein the polysilicon contact includes a titanium nitride barrier layer overlying the polysilicon contact, and rhodium stuffed with silicon oxide barrier layer overlying the titanium nitride layer and underlying the bottom electrode.    
   
   
       7 . The computer system of  claim 6 , wherein the high dielectric layer comprises: 
 a tantalum oxide layer formed by annealing the tantalum oxide layer to temperatures in the range of about 450° C. to 850° C. in an oxygen-containing atmosphere.    
   
   
       8 . The computer system of  claim 6 , wherein the oxygen barrier layer is about 50 to 5000 Å thick.  
   
   
       9 . The computer system of  claim 6 , wherein the tantalum oxide layer is about 50 to 150 Å thick.  
   
   
       10 . The computer system of  claim 6 , wherein the tantalum oxide layer is less than about 150 Å thick.  
   
   
       11 . A computer system, comprising: 
 a computer unit including at least a processor and a memory system in communication with the processor, the memory system including at least one memory device having a memory array including a semiconductor structure having a high dielectric MIM container capacitor and at least one associated transistor device, further comprising:    a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed on the silicon substrate, wherein the bottom electrode comprises iridium;    a high dielectric layer overlying the interior surface of the bottom electrode;    a top electrode overlying the high dielectric layer; and    a polysilicon contact electrically connecting the bottom electrode with the silicon substrate, wherein the polysilicon contact includes a titanium nitride barrier layer overlying the polysilicon contact, and iridium stuffed with silicon oxide barrier layer overlying the titanium nitride layer and underlying the bottom electrode.    
   
   
       12 . The computer system of  claim 11 , wherein the high dielectric layer comprises: 
 a tantalum oxide layer formed by annealing the tantalum oxide layer to temperatures in the range of about 450° C. to 850° C. in an oxygen-containing atmosphere.    
   
   
       13 . The computer system of  claim 11 , wherein the oxygen barrier layer is about 50 to 5000 Å thick.  
   
   
       14 . The computer system of  claim 11 , wherein the tantalum oxide layer is about 50 to 150 Å thick.  
   
   
       15 . A computer system, comprising: 
 a computer unit including at least a processor and a memory system in communication with the processor, the memory system including at least one memory device having a memory array including a semiconductor structure having a high dielectric MIM container capacitor and at least one associated transistor device, further comprising:    a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed on a silicon substrate;    a high dielectric layer overlying the interior surface of the bottom electrode;    a top electrode overlying the high dielectric layer; and    a polysilicon contact electrically connecting the bottom electrode with the silicon substrate, wherein the polysilicon contact includes a titanium nitride barrier layer overlying the polysilicon contact, and iridium stuffed with silicon oxide barrier layer overlying the titanium nitride layer and underlying the bottom electrode.    
   
   
       16 . The computer system of  claim 15 , wherein the high dielectric layer comprises: 
 a tantalum oxide layer formed by annealing the tantalum oxide layer to temperatures in the range of about 450° C. to 850° C. in an oxygen-containing atmosphere.    
   
   
       17 . The computer system of  claim 15 , wherein the oxygen barrier layer is about 50 to 5000 Å thick.  
   
   
       18 . A computer system, comprising: 
 a computer unit including at least a processor and a memory system in communication with the processor, the memory system including at least one memory device having a memory array including a semiconductor structure having a high dielectric MIM container capacitor and at least one associated transistor device, further comprising:    a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed on a silicon substrate, wherein the bottom electrode comprises a noble metal;    a high dielectric layer overlying the interior surface of the bottom electrode;    a top electrode overlying the high dielectric layer; and    a polysilicon contact electrically connecting the bottom electrode with the silicon substrate, wherein the polysilicon contact includes a titanium nitride barrier layer overlying the polysilicon contact, and a noble metal stuffed with silicon oxide barrier layer overlying the titanium nitride layer and underlying the bottom electrode.    
   
   
       19 . The computer system of  claim 18 , wherein the high dielectric layer comprises: 
 a tantalum oxide layer formed by annealing the tantalum oxide layer to temperatures in the range of about 450° C. to 850° C. in an oxygen-containing atmosphere.    
   
   
       20 . The computer system of  claim 18 , wherein the oxygen barrier layer is about 50 to 5000 Å thick.  
   
   
       21 . The computer system of  claim 18 , wherein the noble metal is selected from the group consisting of platinum, iridium, and rhodium.  
   
   
       22 . A semiconductor wafer having a plurality of die formed within the wafer, one or more of the die comprising: 
 a substrate portion;    an oxygen barrier layer including platinum stuffed with silicon oxide overlying the substrate portion;    a bottom platinum electrode layer overlying the oxygen barrier layer;    a tantalum oxide dielectric layer overlying the bottom platinum electrode layer; and    a top electrode overlying the tantalum oxide dielectric layer.    
   
   
       23 . The semiconductor wafer of  claim 22 , wherein the tantalum oxide layer is deposited by annealing the tantalum oxide layer to temperatures in the range of about 450° C. to 850° C. in an oxygen-containing atmosphere.  
   
   
       24 . The semiconductor wafer of  claim 22 , wherein the oxygen barrier layer is about 50 to 5000 Å thick.  
   
   
       25 . A memory system, comprising: 
 one or more memory devices each including a plurality of memory cells having at least one transistor device, further comprising:    a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed in a silicon substrate, wherein the bottom electrode is made of platinum;    a high dielectric layer overlying the interior surface of the bottom electrode;    a top electrode overlying the high dielectric layer; and    a polysilicon contact electrically connecting the bottom electrode with the at least one transistor device, wherein the polysilicon contact includes a titanium nitride barrier layer and a platinum stuffed with silicon oxide barrier layer overlying the polysilicon contact and underlying the bottom electrode.    
   
   
       26 . The memory system of  claim 25 , wherein the high dielectric layer comprises materials selected from the group consisting of tantalum oxide (Ta2O5), strontium titanate (SrTiO3), alumina (Al2O3), hafnium oxide (HfO2), titanium oxide (TiO2), zirconium oxide (ZrO2), barium strontium titanate BaSrTiO3 (BST).  
   
   
       27 . The memory system of  claim 25 , wherein the platinum stuffed with silicon oxide barrier layer is about 50 to 5000 Å thick.  
   
   
       28 . The memory system of  claim 25 , wherein the high dielectric layer is about 50 to 150 Å thick.  
   
   
       29 . A memory system, comprising: 
 one or more memory modules in communication with a memory controller, the memory modules including at least one memory device having a plurality of memory cells arranged in memory arrays, wherein each memory cell includes at least one transistor device in a silicon substrate; further comprising:    a cup-shaped bottom platinum electrode defining an interior surface and an exterior surface within a container formed in the silicon substrate;    a high dielectric layer overlying the interior surface of the bottom electrode;    a top electrode overlying the high dielectric layer; and    a silicon contact, including a titanium nitride barrier layer and a platinum stuffed with silicon oxide barrier layer overlying the silicon contact and underlying the bottom electrode, electrically connects the bottom electrode with the at least one transistor device.    
   
   
       30 . The memory system of  claim 29 , wherein the transistor device is disposed over an active region surrounded by an isolation region in the silicon substrate.  
   
   
       31 . The memory system of  claim 29 , wherein the transistor device comprises: 
 a gate oxide layer over the active region; and    a gate electrode stack over the gate oxide layer.    
   
   
       32 . The memory system of  claim 29 , wherein the platinum stuffed with silicon oxide barrier layer is about 50 to 5000 Å thick.  
   
   
       33 . The memory system of  claim 29 , wherein the silicon contact is a polysilicon contact.  
   
   
       34 . A semiconductor device, comprising: 
 a plurality of transistor devices;    a plurality of high dielectric MIM storage cell capacitors, wherein each capacitor comprises:    an oxygen barrier layer, including platinum stuffed with silicon oxide overlying a silicon substrate;    a bottom platinum electrode layer overlying the oxygen barrier layer;    a tantalum oxide dielectric layer overlying the bottom platinum electrode layer; and    a top electrode overlying the tantalum oxide dielectric layer.    
   
   
       35 . The semiconductor device of  claim 34 , wherein the top electrode is made from platinum.  
   
   
       36 . A semiconductor structure including a high dielectric MIM container capacitor on a silicon substrate, comprising: 
 a cup shaped bottom electrode defining an interior surface and an exterior surface within a container formed on the silicon substrate, wherein the bottom electrode comprises platinum;    a high dielectric layer overlying the interior surface of the bottom electrode;    a top electrode overlying the high dielectric layer; and    a polysilicon contact electrically connecting the bottom electrode with a buried electrical contact on the silicon substrate;    wherein the polysilicon contact includes a titanium nitride barrier layer overlying the polysilicon contact, and platinum stuffed with silicon oxide barrier layer overlying the titanium nitride layer and underlying the bottom electrode.    
   
   
       37 . The semiconductor structure of  claim 36 , wherein forming the high dielectric insulator layer further comprises: 
 annealing the formed high dielectric insulator layer to temperatures of about 450° C. to 850° C. in an oxygen containing atmosphere.    
   
   
       38 . The semiconductor structure of  claim 36 , wherein the oxygen barrier layer is about 50 to 5000 Å thick.