Memory controller

Abstract

A memory controller includes a plurality of buffers and a controller. The buffers are connected with a predetermined memory. The controller issues a first command before all the buffers store data. The first command is an instruction to activate a row address corresponding to a predetermined memory region in the predetermined memory, and it is generated based on a write command input from an external unit. The write command is an instruction to activate a write data to the predetermined memory.

1 . A memory controller comprising: 
 a plurality of buffers configured to connect with a predetermined memory; and    a controller configured to issue a first command before all the buffers store data, the first command comprising an instruction to activate a row address corresponding to a predetermined memory region in the predetermined memory, and being generated based on a write command input from an external unit that will activate write data to the predetermined memory.    
     
     
         2 . The memory controller according to  claim 1 , wherein 
 the controller is configured to issue the first command before initial data of the write data is stored in one of the buffers.    
     
     
         3 . The memory controller according to  claim 2 , further comprising: 
 a counter configured to count the number of data stored in the buffers, and    wherein the controller will determine whether or not data to be written in the buffers is the initial data based on the count value of the counter.    
     
     
         4 . The memory controller according to  claim 1 , wherein 
 the controller is configured to issue a second command for activating a column address corresponding to the predetermined memory region when the same number of data as the number of the buffers are written in the buffers.    
     
     
         5 . The memory controller according to  claim 2 , wherein 
 the controller is configured to issue a second command for activating a column address corresponding to the predetermined memory region when the same number of data as the number of the buffers are written in the buffers.    
     
     
         6 . The memory controller according to  claim 3 , wherein 
 the controller is configured to issue a second command for activating a column address corresponding to the predetermined memory region when the same number of data as the number of the buffers are written in the buffers.    
     
     
         7 . The memory controller according to  claim 4 , further comprising: 
 a clock controller configured to turn OFF the predetermined memory during a period of time from when the first command is issued to when the second command is issued.