Delay cell of voltage controlled delay line using digital and analog control scheme

Abstract

Provided is an analog/digital control delay locked loop (DLL). The DLL includes a phase detector for detecting a phase difference between an input clock signal and a feedback signal to provide an up detection signal or a down detection signal, a charge pump for generating an adjusted output current based on the up or down signals, a loop filter for low pass-filtering the output current to produce an analog control voltage, a voltage controlled delay Line (VCDL) for receiving the analog control voltage, the input clock signal and a digital code, and delaying the input clock signal based on the analog control voltage and the digital code to provide an output clock signal, a delay replica modeling unit formed by replica of delay factors for producing the feedback signal depending on the output clock signal, and a digital code generator for generating the digital code.

1 . A delay cell of a voltage controlled delay line (VCDL), comprising: 
 a differential input transistor unit for receiving an differential input clock signal;    an analog control transistor unit receiving a power supply terminal for adjusting a first delay amount in response to an analog control voltage; and    a digital control transistor unit connected between the analog control transistor unit and the differential input transistor unit for adjusting a second delay amount in response to a digital code, wherein said first delay amount is less than said second delay amount.    
   
   
       2 . The delay cell of VCDL as recited in  claim 1 , further comprising first and second output nodes connected to each drain of a plurality of transistors included in the differential input transistor unit for generating differential output clock signals, respectively.  
   
   
       3 . The delay cell of VCDL as recited in  claim 2 , wherein the analog control transistor unit includes: 
 an analog control load transistor circuit whose one terminal is connected to the power supply terminal, driven in response to a first analog control voltage; and    an analog control current source transistor circuit whose one terminal is connected to a ground voltage terminal, driven in response to a second analog control voltage.    
   
   
       4 . The delay cell of VCDL as recited in  claim 3 , wherein the digital control transistor unit includes: 
 a digital control load transistor circuit connected between the other terminal of the analog control load transistor circuit and the first and second output nodes, driven in response to the digital code; and    a digital control current source transistor circuit connected between a common source of the differential input transistor unit and the analog control current source transistor circuit, driven in response to a complementary value of the digital code.    
   
   
       5 . The delay cell of VCDL as recited in  claim 3 , wherein the analog control load transistor circuit includes a plurality of unit symmetrical loads having a symmetrical structure with respect to the first and second output nodes.  
   
   
       6 . The delay cell of VCDL as recited in  claim 5 , wherein each of the unit symmetrical loads has a pair of transistors with a first transistor taking the first analog voltage via a gate and the other transistor whose gate and drain are commonly connected.  
   
   
       7 . The delay cell of VCDL as recited in  claim 6 , wherein the digital control load transistor circuit is controlled by a digital code of bit number that corresponds to the unit symmetrical loads.  
   
   
       8 . The delay cell of VCDL as recited in  claim 7 , wherein the digital control load transistor circuit includes a plurality of transistors that corresponds to the number of transistors included in the analog control load transistor circuit.  
   
   
       9 . The delay cell of VCDL as recited in  claim 8 , wherein each transistor of the digital control load transistor circuit, which corresponds to the unit symmetrical loads of the analog control load transistor circuit, receives a same code via a gate.  
   
   
       10 . The delay cell of VCDL as recited in  claim 2 , wherein the analog control current source transistor circuit includes a plurality of transistors that corresponds to the number of unit symmetrical loads of the analog control load transistor circuit.  
   
   
       11 . The delay cell of VCDL as recited in  claim 10 , wherein the digital control current source transistor circuit includes a plurality of transistors that corresponds to the number of transistors included in the analog control current source transistor circuit.  
   
   
       12 . An analog/digital control delay locked loop (DLL) comprising: 
 a phase detector for receiving an input clock signal and a feedback signal and detecting a phase difference between the two signals to provide one of an up detection signal and a down detection signal;    a charge pump for receiving one of the up detection signal and the down detection signal and generating an adjusted output current based on the signals;    a loop filter for low pass-filtering the output current to produce an analog control voltage;    a voltage controlled delay line (VCDL) for receiving the analog control voltage, the input clock signal and a digital code, and delaying the input clock signal based on the analog control voltage and the digital code to generate an output clock signal;    a delay replica modeling unit formed by replicas of a delay factor for receiving the output clock signal and producing the feedback signal; and    a digital code generator for generating the digital code.    
   
   
       13 . The analog/digital control DLL as recited in  claim 12 , wherein the digital code generator is implemented by a fuse option.  
   
   
       14 . The analog/digital control DLL as recited in  claim 12 , wherein the digital code generator is implemented by a register control.  
   
   
       15 . The analog/digital control DLL as recited in  claim 12 , wherein the digital code generator is implemented with a digital filter.  
   
   
       16 . The analog/digital control DLL as recited in  claim 12 , wherein the VCDL includes a plurality of delay cells connected in series, and 
 each delay cell includes:    a differential input transistor unit for receiving differential input clock signals;    an analog control transistor unit whose one terminal is connected to a power supply terminal for adjusting a first delay amount in response to analog control voltages; and    a digital control transistor unit connected between the analog control transistor unit and the differential input transistor unit for adjusting a second delay amount in response to a digital code, wherein said first delay amount is less than said second delay amount.    
   
   
       17 . The analog/digital control DLL as recited in  claim 16 , further comprising first and second output nodes connected to each drain of a plurality of transistors included in the differential input transistor unit for generating differential output clock signals, respectively.  
   
   
       18 . The analog/digital control DLL as recited in  claim 17 , wherein the analog control transistor unit includes: 
 an analog control load transistor circuit whose one terminal is connected to the power supply terminal, being driven in response to a first analog control voltage; and    an analog control current source transistor circuit whose one terminal is connected to a ground voltage terminal, being driven in response to a second analog control voltage.    
   
   
       19 . The analog/digital control DLL as recited in  claim 18 , wherein the digital control transistor unit includes: 
 a digital control load transistor circuit connected between the other terminal of the analog control load transistor circuit and the first and second output nodes, driven in response to the digital code; and    a digital control current source transistor circuit connected between the common source of the differential input transistor unit and the analog control current source transistor circuit, driven in response to a complementary value of the digital code.    
   
   
       20 . The analog/digital control DLL as recited in  claim 18 , wherein the analog control load transistor circuit includes a plurality of unit symmetrical loads having a symmetrical structure with respect to the first and second output nodes.  
   
   
       21 . The analog/digital control DLL as recited in  claim 20 , wherein each of the unit symmetrical loads has a pair of transistors with a first transistor taking the first analog voltage via a gate and the other transistor whose gate and drain are commonly connected.  
   
   
       22 . The analog/digital control DLL as recited in  claim 21 , wherein the digital control load transistor circuit is controlled by a digital code of bit number that corresponds to the unit symmetrical loads.  
   
   
       23 . The analog/digital control DLL as recited in  claim 22 , wherein the digital control load transistor circuit includes a plurality of transistors that corresponds to the number of transistors included in the analog control load transistor circuit.  
   
   
       24 . The analog/digital control DLL as recited in  claim 23 , wherein each transistor of the digital control load transistor circuit, which corresponds to the unit symmetrical load of the analog control load transistor circuit, receives a same code via a gate.  
   
   
       25 . The analog/digital control DLL as recited in  claim 17 , wherein the analog control current source transistor circuit includes a plurality of transistors that corresponds to the number of the unit symmetrical loads of the analog control load transistor circuit.  
   
   
       26 . The analog/digital control DLL as recited in  claim 25 , wherein the digital control current source transistor circuit includes a plurality of transistors that corresponds to the number of transistors included in the analog control current source transistor circuit.