Semiconductor device having gate insulating layers with differing thicknesses

Abstract

Semiconductor devices include a first gate pattern on a first active area of a semiconductor substrate. The first gate pattern has a top width that is substantially the same as or less than a bottom width of the first gate pattern. A second gate pattern is provided on a second active area of the semiconductor substrate. The second gate pattern has a top width that is wider than a bottom width of the second gate pattern. Semiconductor device are fabricated by forming a first gate pattern on a first gate insulation layer formed on a first active region of a semiconductor substrate. A mask insulation layer is formed on the semiconductor substrate that includes the first gate pattern. First and second gate openings respectively exposing second and third active regions of the semiconductor substrate are formed by patterning the mask insulation layer. Second and third gate insulation layers respectively are formed on second and third active regions exposed in the first and second gate openings. Second and third gate patterns are formed in the first and second gate openings respectively and the mask insulation layer is removed.

1 . A semiconductor device comprising: 
 a first gate pattern on a first active area of a semiconductor substrate, the first gate pattern having a top width that is substantially the same as or less than a bottom width of the first gate pattern; and    a second gate pattern on a second active area of the semiconductor substrate, the second gate pattern having a top width that is wider than a bottom width of the second gate pattern.    
   
   
       2 . The semiconductor device of  claim 1 , further comprising a third gate pattern on a third active area of the semiconductor substrate, the third gate pattern having a top width that is wider than a bottom width of the third gate pattern.  
   
   
       3 . The semiconductor device of  claim 2 , further comprising: 
 a first gate insulating layer disposed between the first gate pattern and the first active area and having a first thickness;    a second gate insulating layer disposed between the second gate pattern and the second active area and having a second thickness that is greater than the first thickness of the first gate insulating layer; and    a third gate insulating layer disposed between the third gate pattern and the third active area and having a third thickness that is greater than the second thickness of the second gate insulating layer.    
   
   
       4 . The semiconductor device of  claim 2 , further comprising respective silicide layers on the first gate pattern, the second gate pattern and the third gate pattern.  
   
   
       5 . The semiconductor device of  claim 2 , further comprising impurity diffusion regions in respective ones of the first, second and third active regions adjacent sides of the first, second and third gate patterns.  
   
   
       6 . The semiconductor device of  claim 2 , wherein the second and third gate patterns further comprise: 
 a conductive adhesion layer having a substantially “U” shaped cross section; and    a metal layer in a gap region of the conductive adhesion layer.