Ultra high density flash memory

Abstract

Various aspects related to a method of reading a non-volatile memory cell adapted to store a first bit and a second bit. Various method embodiments comprise reading the first bit, including applying a first voltage level to a first node of the memory cell and a second voltage level to a second node of the memory cell, and further comprise reading the second bit, including applying the first voltage level to the second node and applying the second voltage level to the first node.

1 . A method of reading a non-volatile memory cell coupled to receive a first signal and a second signal and storing a first bit and a second bit, the method comprising: 
 reading the first bit, including applying a first voltage level to the first signal and a second voltage level to the second signal; and    reading the second bit, including applying the first voltage level to the second signal and applying the second voltage level to the first signal.    
   
   
       2 . The method of  claim 1 , wherein the first signal includes a first control gate signal for a first control gate of the memory cell, and the second signal includes a second control gate signal for a second control gate of the memory cell.  
   
   
       3 . The method of  claim 1 , further comprising performing a flash erase to erase the first bit and the second bit.  
   
   
       4 . A method of reading a non-volatile memory cell adapted to store a first bit and a second bit, comprising: 
 reading the first bit, including applying a first voltage level to a first node of the memory cell and a second voltage level to a second node of the memory cell; and    reading the second bit, including applying the first voltage level to the second node and applying the second voltage level to the first node.    
   
   
       5 . The method of  claim 4 , wherein the first node includes a first control gate and the second node includes a second control gate.  
   
   
       6 . The method of  claim 4 , further comprising performing a flash erase to erase the first storage region and the second storage region.  
   
   
       7 . A method of programming a non-volatile memory cell having a first storage region to store a first bit and a second storage region to store a second bit, comprising: 
 programming the first storage region, including applying programming voltages to accelerate electrons to store hot electrons in the first storage region; and    programming the second storage region, including applying programming voltages to accelerate electrons to store hot electrons in the second storage region.    
   
   
       8 . The method of  claim 7 , wherein the first storage region includes a first floating gate separated from a body region of the memory cell by an insulator and the second storage region includes a second floating gate separated from the body region of the memory cell by the insulator.  
   
   
       9 . The method of  claim 7 , further comprising performing a flash erase to erase the first bit and the second bit.  
   
   
       10 . A method of operating a non-volatile memory cell having a first storage region to store a first bit and a second storage region to store a second bit, comprising: 
 programming the first storage region, including applying programming voltages to accelerate electrons to store hot electrons in the first storage region;    reading the first storage bit, including applying a first voltage level to a first node of the memory cell and a second voltage level to a second node of the memory cell;    programming the second storage region, including applying programming voltages to accelerate electrons to store hot electrons in the second storage region; and    reading the second storage bit, including applying the first voltage level to the second node and applying the second voltage level to the first node.    
   
   
       11 . The method of  claim 10 , further comprising performing a flash erase to erase the first storage region and the second storage region.  
   
   
       12 . The method of  claim 10 , wherein the first node includes a first control gate of the memory cell and the second node includes a second control gate of the memory cell.  
   
   
       13 . A memory, comprising: 
 a first semiconductor pillar, including a first source/drain region, a second source/drain region, and a body region between the first and second source/drain regions;    a first programmable floating gate storage region separated from the body region of the first semiconductor pillar by a dielectric, the first storage region adapted to store a first bit; and    a second programmable floating gate storage region separated from the body region of the first semiconductor pillar by the dielectric, the second storage region adapted to store a second bit.    
   
   
       14 . The memory of  claim 13 , further comprising: 
 a second semiconductor pillar, the second semiconductor pillar including a first source/drain region, a second source/drain region, and a body region between the first and second source/drain regions;    a third programmable floating gate storage region separated from the body region of the second semiconductor pillar by the dielectric, the third storage region adapted to store a third bit;    a fourth programmable floating gate storage region separated from the body region of the second semiconductor pillar by the dielectric, the fourth storage region adapted to store a fourth bit; and    a word line disposed between the first and second semiconductor pillars, the word line being positioned to function as a first control gate for a first transistor that includes the body region and the first and second source/drain regions of the first semiconductor pillar and being positioned to function as a second control gate for a second transistor that includes the body region and the first and second source/drain regions of the second semiconductor pillar.    
   
   
       15 . The memory of  claim 13 , wherein: 
 the first programmable floating gate storage region includes a first floating gate separated from the body region of the first semiconductor pillar by the dielectric; and    the second programmable floating gate storage region includes a second floating gate separated from the body region of the first semiconductor pillar by the gate dielectric, the second storage region adapted to store a second bit.    
   
   
       16 . The memory of  claim 15 , further comprising a third floating gate separated from the body region of the first semiconductor pillar by the dielectric, and a fourth floating gate separated from the body region of the first semiconductor pillar by the dielectric.  
   
   
       17 . A memory, comprising: 
 a pillar of semiconductor material that extends outwardly from a working surface of a substrate to form a first source/drain region, a second source/drain region, and a body region between the first and second source/drain regions;    at least two floating charge storing regions separated from the body region by a dielectric; and    a number of control gates, each control gate being associated with at least one floating charge storing region so as to allow selective storage and retrieval of data on the floating charge storing regions.    
   
   
       18 . The memory of  claim 17 , wherein the at least two floating charge storing regions includes two charge storing regions.  
   
   
       19 . The memory of  claim 17 , wherein the at least two floating charge storing regions includes at least two floating gates separated from the body region by the dielectric.  
   
   
       20 . The memory of  claim 17 , further comprising: 
 a second pillar of semiconductor material that extends outwardly from a working surface of a substrate to form a first source/drain region, a second source/drain region, and a body region between the first and second source/drain regions, at least two floating charge storing regions separated from the body region of the second pillar by a dielectric, and a number of control gates, each control gate being associated with at least one floating charge storing region separated from the body region of the second pillar by the dielectric so as to allow selective storage and retrieval of data on the floating charge storing regions; and    a word line positioned between the pillars to function as at least one of the control gates.    
   
   
       21 . A memory, comprising: 
 a first semiconductor pillar, including a first source/drain region, a second source/drain region, and a body region between the first and second source/drain regions; and    at least one control gate, at least two charge storing regions disposed between the body region and the at least one control gate, the at least two charge storing regions being separated from the body region by a gate dielectric and the at least one control gate being separated from the at least two charge storing regions by an intergate dielectric, the at least two charge storing regions being adapted to store a first bit and a second bit.    
   
   
       22 . The memory of  claim 21 , wherein the at least two charge storing regions includes a floating gate adapted to store two bits.  
   
   
       23 . The memory of  claim 22 , wherein the floating gate adapted to store two bits is adapted to store four charge states.  
   
   
       24 . A memory, comprising: 
 means for programming a first storage bit of a memory cell;    means for programming a second storage bit of the memory cell;    means for reading the first storage bit of the memory cell; and    means for reading the second storage bit of the memory cell.    
   
   
       25 . The memory of  claim 24 , wherein: 
 the means for programming the first storage bit of the memory cell includes means for applying programming voltages to accelerate electrons to store hot electrons in a corresponding first storage region of the memory cell;    the means for programming the second storage bit of the memory cell includes means for applying programming voltages to accelerate electrons to store hot electrons in a corresponding second storage bit;    the means for reading the first storage bit of the memory cell includes means for applying a first voltage level to a first node of the memory cell and a second voltage level to a second node of the memory cell; and    the means for reading the second storage bit includes means for applying the first voltage level to the second node and applying the second voltage level to theu first node.