Dynamic random access memory of semiconductor device and method for manufacturing the same

Abstract

The present invention discloses an improved DRAM of semiconductor device and method for manufacturing the same wherein an ONO (oxide-nitride-oxide) structure for trapping electrons or holes used in a non-volatile memory is employed in a gate insulating film of the DRAM to reduce impurity concentrations of a channel region and a well region.

1 - 14 . (canceled)  
   
   
       15 . A DRAM of semiconductor device, comprising: 
 a semiconductor substrate having a first region and a second region, the second region including a pMOS region and an nMOS region;    a stacked structure of a lower gate oxide film and an intermediate gate insulating film including an electron/hole trap disposed at least on the first region of the first region and the pMOS region of the second region;    a stacked structure of an upper gate oxide film and a gate electrode pattern disposed on the intermediate gate insulating film and at least on the semiconductor substrate in the nMOS region of the pMOS region and the nMOS region of the second region; and    a channel region disposed in the semiconductor substrate under below the gate electrode pattern.    
   
   
       16 . The DRAM of semiconductor device according to  claim 15 , further comprising a source/drain region in the semiconductor substrate at both sides of the gate electrode pattern.  
   
   
       17 . The DRAM of semiconductor device according to  claim 15 , wherein the first and the second regions comprise a cell region and a core/peripheral circuit region, respectively.  
   
   
       18 . The DRAM of semiconductor device according to  claim 15 , wherein the intermediate gate insulating film is selected from a group consisting of a nitride film, an Al 2 O 3  film, an HfO 2  film and combinations thereof.  
   
   
       19 . The DRAM of semiconductor device according to  claim 15 , wherein the gate electrode pattern comprises a stacked structure of a lower conductive layer selected from a group consisting of a polysilicon film and a polycrystalline SiGe film, and an upper conductive layer selected from a group consisting of WSi x  layer, NiSi x , layer, CoSi x  layer, WN/W layer and TiN/W layer and a CVD insulating film.  
   
   
       20 . The DRAM of semiconductor device according to  claim 15 , a thickness of the lower gate oxide film is equal to or less than 100 Å, a thickness of the intermediate gate insulating film ranges from 5 to 100 Å, a thickness of the upper gate oxide film in the first region is equal to or less than 100 Å, and a thickness of the upper gate oxide film in the second region ranges from 10 to 400 Å.