US2007065995A1PendingUtilityA1

Semiconductor device and method of manufacturing the same

Assignee: SEMICONDUCTOR ENERGY LABPriority: Apr 27, 2001Filed: Oct 23, 2006Published: Mar 22, 2007
Est. expiryApr 27, 2021(expired)· nominal 20-yr term from priority
Inventors:Tatsuya Arao
H10P 95/90H10D 86/60H10D 86/441H10D 30/6733H10D 86/421H10D 86/0221H10D 86/40H10D 84/83H10D 30/6758H10D 30/6757H10D 30/6739H10D 30/6723H10D 30/6715H10D 30/794H10D 30/791H10D 30/0321H10D 30/0314G02F 1/136227G02F 1/1341G02F 1/134309G02F 1/136286G02F 1/13394G02F 1/136209G02F 1/1368G02F 1/13392H10K 59/12G02F 1/1339
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Claims

Abstract

There has been a case where peeling occurs if an internal stress of a wiring of a TFT is strong. In particular, the internal stress of a gate electrode largely influences a stress that a semiconductor film receives, and there has been a case where the internal stress becomes a cause of reduction in electric characteristics of a TFT depending on the internal stress. According to the present invention, an impurity element is introduced into a wiring, or both the introduction of an impurity element and heat treatment are performed, whereby the wiring can be controlled to have a desired internal stress. It is effective that the present invention is particularly applied to a gate electrode. Further, it is possible that the introduction of an impurity element and the heat treatment are conducted to only a desired region to conduct control to attain a desired internal stress.

Claims

exact text as granted — not AI-modified
1 . A method of manufacturing a semiconductor device, comprising: 
 forming a semiconductor film over an insulating surface;    forming an insulating film over the semiconductor film;    forming a conductive film electrically connected to the semiconductor film over the insulating film;    introducing an impurity element into the conductive film;    selectively etching the conductive film to form wirings by using photolithography, and    wherein the wirings comprising the conductive film are used as source and drain wirings of a TFT.    
   
   
       2 . The method according to  claim 1 , wherein the impurity element comprises at least one selected from impurity elements imparting n-type conductivity, impurity elements imparting p-type conductivity, and rare gas elements.  
   
   
       3 . The method according to  claim 1 , wherein the impurity element is introduced by at least one selected from the group consisting of a plasma doping method, an ion implantation method and an ion shower doping method.  
   
   
       4 . A method according to  claim 1 , wherein the semiconductor film is a semiconductor film having a crystalline structure.  
   
   
       5 . A method of manufacturing a semiconductor device, comprising: 
 forming a P-type well and an N-type well in a semiconductor substrate;    forming a first insulating film over the P-type well and the N-type well;    forming gate electrodes over the first insulating film;    forming a second insulating film over the gate electrodes;    forming a conductive film electrically connected to the P-type well and the N-type well over the second insulating film;    introducing an impurity element into the conductive film;    selectively etching the conductive film to form wirings, and    wherein the wirings comprising the conductive film are used as source and drain wirings of an n-channel MOSFET and are used as source and drain wirings of a p-channel MOSFET.    
   
   
       6 . The method according to  claim 5 , wherein the impurity element comprises at least one selected from impurity elements imparting n-type conductivity, impurity elements imparting p-type conductivity, and rare gas elements.  
   
   
       7 . The method according to  claim 5 , wherein the impurity element is introduced by at least one selected from the group consisting of a plasma doping method, an ion implantation method and an ion shower doping method.  
   
   
       8 . The method according to  claim 5 , wherein the wirings are formed by using photolithography.  
   
   
       9 . The method according to  claim 5 , wherein the gate electrodes are introduced an impurity element.

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