NAND memory arrays

Abstract

A NAND memory array has a plurality of rows of memory cells and a plurality of columns of NAND strings of memory cells. Each NAND string is selectively connected to a bit line through a drain select gate of the respective column. Each of the drain select gates has a first dielectric layer formed on a semiconductor substrate of the memory array and a control gate formed on the first dielectric layer. Each of the memory cells of each of the NAND strings has a second dielectric layer formed on the substrate adjacent the first dielectric layer, a floating gate formed on the second dielectric layer, a third dielectric layer formed on the floating gate, and a control gate formed on the third dielectric layer. The first dielectric layer is thicker than the second dielectric layer.

1 . A NAND memory array comprising: 
 a plurality of rows of memory cells; and    a plurality of columns of NAND strings of memory cells, each NAND string selectively connected to a bit line through a drain select gate of the respective column;    wherein each of the drain select gates comprises a first dielectric layer formed on a semiconductor substrate of the memory array and a control gate formed on the first dielectric layer; and    wherein each of the memory cells of each of the NAND strings comprises a second dielectric layer formed on the substrate adjacent the first dielectric layer, a floating gate formed on the second dielectric layer, a third dielectric layer formed on the floating gate, and a control gate formed on the third dielectric layer, wherein the first dielectric layer is thicker than the second dielectric layer.    
   
   
       2 . The NAND memory array of  claim 1 , wherein the first and second dielectric layers are thermal oxide layers.  
   
   
       3 . The NAND memory array of  claim 2 , wherein the second dielectric layer is a nitride-containing thermal oxide layer.  
   
   
       4 . The NAND memory array of  claim 1 , wherein second dielectric layer adjoins the first dielectric layer.  
   
   
       5 . A NAND memory array comprising: 
 a plurality of rows of memory cells; and    a plurality of columns of NAND strings of memory cells, each NAND string selectively connected to a bit line through a drain select gate of the respective column;    wherein each of the drain select gates comprises a first dielectric layer formed on a semiconductor substrate of the memory array and a first conductive layer formed on the first dielectric layer;    wherein each of the memory cells of each of the NAND strings comprises a second dielectric layer formed on the substrate adjacent the first dielectric layer and the first conductive layer formed on the second dielectric layer, wherein the first dielectric layer is thicker than the second dielectric layer; and    wherein each of the drain select gates and each of the memory cells of each of the NAND strings further comprises a third dielectric layer formed on the first conductive layer and a second conductive layer formed on the third dielectric layer.    
   
   
       6 . The NAND memory array of  claim 5 , wherein the first and second dielectric layers are thermal oxide layers.  
   
   
       7 . The NAND memory array of  claim 6 , wherein the second dielectric layer is a nitride-containing thermal oxide layer.  
   
   
       8 . The NAND memory array of  claim 5 , wherein the first conductive layer is a polysilicon layer.  
   
   
       9 . The NAND memory array of  claim 5 , wherein, the second conductive layer is selected from the group consisting of a polysilicon layer, a metal layer, a metal-containing layer, a layer containing one or more conductive materials, and one or more conductive layers.  
   
   
       10 . The NAND memory array of  claim 5 , wherein the third dielectric layer comprises one or more layers of dielectric material, an oxide layer, a nitride layer, or an oxide-nitride-oxide layer.  
   
   
       11 . The NAND memory array of  claim 5 , wherein second dielectric layer adjoins the first dielectric layer.  
   
   
       12 . A NAND memory array comprising: 
 a plurality of rows of memory cells; and    a plurality of columns of NAND strings of memory cells, each NAND string selectively connected to a bit line through a drain select gate of the respective column;    wherein each of the drain select gates comprises a first oxide layer formed on a semiconductor substrate of the memory array and a polysilicon layer formed on the oxide layer;    wherein each of the memory cells of each of the NAND strings comprises a nitride-containing second oxide layer formed on the substrate adjacent the first oxide layer and the polysilicon layer formed on the nitride-containing second oxide layer, wherein the first oxide layer is thicker than the nitride-containing second oxide layer; and    wherein each of the drain select gates and each of the memory cells of each of the NAND strings further comprises a dielectric layer formed on the polysilicon layer, and a conductive layer formed on the dielectric layer.    
   
   
       13 . The NAND memory array of  claim 12 , wherein the conductive layer is selected from the group consisting of a second polysilicon layer, a metal layer, a metal-containing layer, a layer containing one or more conductive materials, and one or more conductive layers.  
   
   
       14 . The NAND memory array of  claim 12 , wherein the dielectric layer comprises one or more layers of dielectric material, a third oxide layer, a nitride layer, or an oxide-nitride-oxide layer.  
   
   
       15 . The NAND memory array of  claim 12 , wherein the nitride-containing second oxide layer adjoins the first oxide layer.  
   
   
       16 . A memory device comprising: 
 a memory array comprising: 
 a plurality of rows of memory cells, each row connected to a word line; and  
 a plurality of columns of NAND strings of memory cells, each NAND string selectively connected to a bit line through a drain select gate of the respective column;  
 wherein each of the drain select gates comprises a first dielectric layer formed on a semiconductor substrate of the memory array and a control gate formed on the first dielectric layer; and  
 wherein each of the memory cells of each of the NAND strings comprises a second dielectric layer formed on the substrate adjacent the first dielectric layer, a floating gate formed on the second dielectric layer, a third dielectric layer formed on the floating gate, and a word line formed on the third dielectric layer, wherein the first dielectric layer is thicker than the second dielectric layer;  
   column access circuitry connected to the bit lines; and    row access circuitry connected to the word lines.    
   
   
       17 . The memory device of  claim 16 , wherein second dielectric layer adjoins the first dielectric layer.  
   
   
       18 . A memory device comprising: 
 a memory array comprising: 
 a plurality of rows of memory cells, each row connected to a word line; and  
 a plurality of columns of NAND strings of memory cells, each NAND string selectively connected to a bit line through a drain select gate of the respective column;  
 wherein each of the drain select gates comprises a first dielectric layer formed on a semiconductor substrate of the memory array and a first conductive layer formed on the first dielectric layer;  
 wherein each of the memory cells of each of the NAND strings comprises a second dielectric layer formed on the substrate adjacent the first dielectric layer and the first conductive layer formed on the second dielectric layer, wherein the first dielectric layer is thicker than the second dielectric layer; and  
 wherein each of the drain select gates and each of the memory cells of each of the NAND strings further comprises a third dielectric layer formed on the first conductive layer, and a second conductive layer formed on the third dielectric layer;  
   column access circuitry connected to the bit lines; and    row access circuitry connected to the word lines.    
   
   
       19 . The memory device of  claim 18 , wherein the first and second dielectric layers are thermal oxide layers.  
   
   
       20 . The memory device of  claim 19 , wherein the second dielectric layer is a nitride-containing thermal oxide layer.  
   
   
       21 . The memory device of  claim 18 , wherein second dielectric layer adjoins the first dielectric layer.