Storage controller, data processing method and computer program product

Abstract

When a first channel processor from among a plurality of channel processors receives an I/O request from a host system, a second channel processor, which is to execute a part of the processing to respond to the I/O request, is selected from among the channel processors based on the LM directories of the respective channel processors. The selected second channel processor checks whether there is a cache hit. If there is a cache hit, it transfers the data from the cache memory to the buffer memory. The first channel processor then processes the I/O request using the data transferred to the buffer memory.

1 . A storage controller comprising: 
 a plurality of channel processors for processing an I/O request from a host system;    a cache memory for temporarily storing, in cache slots, data that is read and written by the channel processors in response to I/O requests from the host system;    a local memory assigned to each of the channel processors for storing management information indicating whether or not data read and written by the relevant channel processor exists in the cache slot; and    a buffer memory for storing data transmitted between the channel processors,    wherein, when a first channel processor from among the channel processors receives an I/O request from the host system, it selects, based on the management information stored in the local memories of the respective channel processors, a second channel processor from among the channel processors, which is to execute a part of the processing to respond to the I/O request; the second channel processor checks whether there is a cache hit, and if there is a cache hit, it transfers the data from the cache memory to the buffer memory; and the first channel processor processes the I/O request using the data transferred to the buffer memory.    
   
   
       2 . A storage controller comprising: 
 a plurality of channel processors for processing an I/O request from a host system;    a cache memory for temporarily storing, in cache slots, data that is read and written by the channel processors in response to I/O requests from the host system; and    a buffer memory for storing data transmitted between the channel processors,    wherein, when a first channel processor from among the channel processors receives an I/O request from the host system, it selects, based on the address of the data requested by the host system or the access pattern of the host system, a second channel processor from among the channel processors, which is to execute a part of processing to respond to the I/O request; the second channel processor checks whether there is a cache hit, and if there is a cache hit, it transfers the data from the cache memory to the buffer memory; and the first channel processor processes the I/O request using the data transferred to the buffer memory.    
   
   
       3 . A data processing method comprising: 
 a step where a first channel processor from among a plurality of channel processors receives an I/O request from a host system;    a step where a second channel processor is selected from among the channel processors based on management information indicating whether data read and written by the channel processors exist in cache slots, the second channel processor being one to execute a part of processing to respond to the I/O request;    a step where the second channel processor checks whether there is a cache hit, and if there is a cache hit, it transfers the data from a cache memory to a buffer memory; and    a step where the first channel processor processes the I/O request using the data transferred to the buffer memory.    
   
   
       4 . A data processing method comprising: 
 a step where a first channel processor from among a plurality of channel processors receives an I/O request from a host system;    a step where a second channel processor is selected from among the channel processors based on the address of data requested by the host system or the access pattern of the host system, the second channel processor being one to execute a part of processing to respond to the I/O request;    a step where the second channel processor checks whether there is a cache hit, and if there is a cache hit, it transfers the data from a cache memory to a buffer memory; and    a step where the first channel processor processes the I/O request using the data transferred to the buffer memory.    
   
   
       5 . A computer program product having a computer program for making a storage controller execute the data processing according to  claim 3 .  
   
   
       6 . A computer program product having a computer program for making a storage controller execute the data processing according to  claim 4.