Method of fabricating lanthanum oxide layer and method of fabricating MOSFET and capacitor using the same

Abstract

Methods of fabricating a lanthanum oxide layer, and methods of fabricating a MOSFET and/or a capacitor especially adapted for semiconductor applications using such a lanthanum oxide layer are disclosed. The methods include a preliminary step of disposing a semiconductor substrate into a chamber. Tris(bis(trimethylsilyl)amino)Lanthanum as a lanthanum precursor is then injected into the chamber such that the lanthanum precursor is chemisorbed on the semiconductor substrate. Then, after carrying out a first purge of the chamber, at least one oxidizer is injected into the chamber such that the oxidizer is chemisorbed with the lanthanum precursor on the semiconductor substrate. Then, the chamber is purged a second time. The described steps of injecting the lanthanum precursor into the chamber, first-purging the chamber, injecting an oxidizer into the chamber, and second-purging the chamber may be sequentially and repeatedly performed to form a lanthanum oxide layer of a desired thickness having enhanced semiconductor characteristics.

1 . A semiconductor device comprising a dielectric layer that at least includes a lanthanum oxide layer fabricated in the semiconductor device in accordance with a method comprising the sequential steps of: 
 a) disposing a semiconductor substrate into a chamber;    b) injecting a lanthanum precursor into the chamber such that a layer of the lanthanum precursor is chemisorbed on the semiconductor substrate, wherein the lanthanum precursor consists essentially of tris(bis(trimethylsilyl)amino) Lanthanum;    c) conducting a first purge of the chamber;    d) injecting at least one oxidizer into the chamber such that the oxidizer is chemisorbed with the lanthanum precursor on the semiconductor substrate;    e) conducting a second purge of the chamber; and,    f) repeating steps (b) through (e) until a lanthanum oxide layer of a desired multi-atomic layer thickness is obtained.    
   
   
       2 . The semiconductor device according to  claim 1 , wherein the step of injecting the lanthanum precursor into the chamber is performed using a bubbler type technique or an injector type technique.  
   
   
       3 . The semiconductor device according to  claim 2 , wherein an injector type technique is used and the solution for dissolving the lanthanum precursor is at least one member selected from the group consisting of THF, THP and TFP.  
   
   
       4 . The semiconductor device according to  claim 1 , wherein the first purge step and the second purge step are performed by passing an inert gas or a nitrogen gas into and through the chamber.  
   
   
       5 . The semiconductor device according to  claim 1 , wherein the oxidizer is at least one member selected from the group consisting of H 2 O, H 2 O 2 , O 3 , O 2 , and N 2 O.  
   
   
       6 . The semiconductor device according to  claim 5 , wherein the oxidizer is activated through a plasma treatment or a ultraviolet ray irradiation treatment.  
   
   
       7 . The semiconductor device according to  claim 1 , wherein the step of injecting the at least one oxidizer into the chamber comprises the sequential steps of: 
 injecting a first oxidizer that includes an —OH group into the chamber;    purging the chamber using an inert gas or a nitrogen gas; and    injecting a second oxidizer that includes O 3  or O 2  into the chamber.    
   
   
       8 . The semiconductor device according to  claim 7 , wherein the first oxidizer is H 2 O and the second oxidizer is O 3 .  
   
   
       9 . A MOSFET element for use in semiconductor applications comprising a gate dielectric layer that at least includes a lanthanum oxide layer formed in accordance with a method of fabricating a MOSFET for the semiconductor applications comprising the sequential steps of: 
 forming an isolation layer to define an active region in a semiconductor substrate;    forming the gate dielectric layer that includes the lanthanum oxide layer on the active region, wherein the lanthanum oxide layer is formed by an ALD technique using tris(bis(trimethylsilyl)amino) Lanthanum as a lanthanum precursor; and    forming a gate electrode crossing the active region on the gate dielectric layer.    
   
   
       10 . The MOSFET element according to  claim 9 , wherein the gate dielectric layer consists of a single layer of a lanthanum oxide layer.  
   
   
       11 . The MOSFET element according to  claim 9 , wherein the gate dielectric layer consists of stacked layers including at least a lanthanum oxide layer and a dielectric layer.  
   
   
       12 . The MOSFET element according to  claim 11 , wherein the dielectric layer is a layer selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a hafnium oxide layer, a zirconium oxide layer, a tantalum oxide layer, a titanium oxide layer, and a stacked layer consisting of combinations thereof.  
   
   
       13 . The MOSFET element according to  claim 9 , further comprising a step of performing an annealing process on the gate dielectric layer before the step of forming the gate electrode.  
   
   
       14 . The MOSFET element according to  claim 13 , wherein the annealing process is performed under vacuum or in the presence of an inert gas.  
   
   
       15 . The MOSFET element according to  claim 13 , wherein the annealing process is performed at a temperature of about 300 to 900° C. and at a pressure equal to or less than 10 −3  Torr.  
   
   
       16 . The MOSFET element according to  claim 9 , Wherein the method further comprises a step of forming source/drain regions in the active region adjacent to the gate electrode after the step of forming the gate electrode.  
   
   
       17 . A capacitor element for use in semiconductor applications comprising a capacitor dielectric layer that at least includes a lanthanum oxide layer formed in accordance with a method of fabricating a capacitor for the semiconductor applications comprising the sequential steps of: 
 forming a lower electrode;    forming the capacitor dielectric layer that includes the lanthanum oxide layer on the lower electrode, wherein the lanthanum oxide layer is formed by an ALD technique using tris(bis(trimethylsilyl)amino) Lanthanum as a lanthanum precursor; and    forming an upper electrode on the capacitor dielectric layer.    
   
   
       18 . The capacitor element according to  claim 17 , wherein the lower electrode is formed as a structure selected from the group consisting of a stack structure, a cylinder structure, and a concave structure.  
   
   
       19 . The capacitor element according to  claim 17 , wherein the lower electrode consists of a conductive layer selected from the group consisting of a metal layer, a metal nitride layer, a metal oxide layer, a metal oxynitride layer, an impurity-doped polysilicon layer, and a stacked layer consisting of combinations thereof.  
   
   
       20 . The capacitor element according to  claim 17 , wherein the capacitor dielectric layer consists of a single layer of a lanthanum oxide layer.  
   
   
       21 . The capacitor element according to  claim 17 , wherein the capacitor dielectric layer consists of stacked layers including at least a lanthanum oxide layer and a dielectric layer.  
   
   
       22 . The capacitor element according to  claim 21 , wherein the dielectric layer is a layer selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a hafnium oxide layer, a zirconium oxide layer, a tantalum oxide layer, a titanium oxide layer, and a stacked layer consisting of combinations thereof.  
   
   
       23 . The capacitor element according to  claim 17 , wherein the upper electrode consists of a conductive layer selected from the group consisting of a metal layer, a metal nitride layer, a metal oxide layer, a metal oxynitride layer, an impurity-doped polysilicon layer, and a stacked layer consisting of combinations thereof.  
   
   
       24 . The capacitor element according to  claim 17 , wherein the method further comprises a step of forming a reaction barrier layer on the lower electrode before the step of forming the dielectric layer including a lanthanum oxide layer.  
   
   
       25 . The capacitor element according to  claim 24 , wherein the reaction barrier layer is formed by treating the lower electrode by means of an RTN (rapid thermal nitridation) process or an RTO (rapid thermal oxidation) process.  
   
   
       26 . The capacitor element according to  claim 24 , wherein the reaction barrier layer is formed of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer using a CVD capacitor element.  
   
   
       27 . The capacitor element according to  claim 17 , wherein the method further comprises a step of performing an annealing process on the capacitor dielectric layer before the step of forming the upper electrode.  
   
   
       28 . The capacitor element according to  claim 27 , wherein the annealing process is performed under vacuum or in the presence of an inert gas.  
   
   
       29 . The capacitor element according to  claim 27 , wherein the annealing process is performed at a temperature of about 300 to 900° C. and at a pressure equal to or less than 10 −3  Torr.