Method for manufacturing thin film transistor, thin film transistor and pixel structure

Abstract

A method for manufacturing a thin film transistor is provided. First, a poly-silicon island is formed on a substrate. Then, a patterned gate dielectric layer and a gate are formed on the poly-silicon island. Next, a source/drain is formed in the poly-silicon island beside the gate, wherein the region between the source/drain is a channel. Furthermore, a metal layer is formed on the substrate to cover the gate, the patterned gate dielectric layer and the poly-silicon island. Moreover, the metal layer above the source/drain will react with the poly-silicon island to form a silicide layer. Then, the non-reacted metal layer is removed. Afterwards, an inter-layer dielectric (ILD) is formed to cover the substrate. Then, the inter-layer dielectric above the source/drain is removed to form a source/drain contacting hole, wherein the silicide layer is used as an etching stopper.

1 . A method for manufacturing thin film transistor comprising: 
 forming a poly-silicon island on a substrate;    forming a patterned gate dielectric layer and a gate on the poly-silicon island;    forming a source/drain in the poly-silicon island beside the gate, wherein a channel is disposed between the source/drain;    forming a metal layer on the substrate to cover the gate, the patterned gate dielectric layer and the poly-silicon island;    forming a silicide layer through the reaction of the metal layer and the poly-silicon island above the source/drain;    removing the non-reacted metal layer;    forming an inter-layer dielectric to cover the substrate; and    removing the inter-layer dielectric above the source/drain to form a source/drain contact hole, wherein the silicide layer is used as a etching stopper.    
   
   
       2 . The method for manufacturing thin film transistor as recited in  claim 1 , wherein the method for forming the poly-silicon island on the substrate comprises: 
 forming an amorphous layer on the substrate;    transforming the amorphous layer into a poly-silicon layer; and    patterning the poly-silicon layer to form the poly-silicon island.    
   
   
       3 . The method for manufacturing thin film transistor as recited in  claim 2 , wherein the method for transforming the amorphous layer into a poly-silicon layer comprises excimer laser annealing (ELA) or rapid thermal annealing (RTA).  
   
   
       4 . The method for manufacturing thin film transistor as recited in  claim 2 , wherein before forming the amorphous layer on the substrate, the method further comprises forming a buffer layer on the substrate.  
   
   
       5 . The method for manufacturing thin film transistor as recited in  claim 4 , wherein the material of the buffer layer comprises silicon nitrides.  
   
   
       6 . The method for manufacturing thin film transistor as recited in  claim 1 , wherein the material of the metal layer is selected from one of palladium (Pd), titanium (Ti), nickel (Ni), TiW, tungsten (W), cobalt (Co), tantalum (Ta), molybdenum (Mo), platinum (Pt), germanium (Ge) and the combination thereof.  
   
   
       7 . The method for manufacturing thin film transistor as recited in  claim 1 , wherein the method for forming the metal layer on the substrate comprises sputtering or plasma deposition.  
   
   
       8 . The method for manufacturing thin film transistor as recited in  claim 1 , wherein the method for forming the silicide layer through the reaction of the metal layer and the poly-silicon island above the source/drain comprises an annealing process.  
   
   
       9 . The method for manufacturing thin film transistor as recited in  claim 1 , wherein the method for removing the non-reacted metal layer comprises a wet etching process.  
   
   
       10 . The method for manufacturing thin film transistor as recited in  claim 1 , wherein the method for removing the inter-layer dielectric above the source/drain comprises a photolithography process and a dry etching with the silicide layer being used as the etching stopper.  
   
   
       11 . The method for manufacturing thin film transistor as recited in  claim 1 , wherein after forming the source/drain contact hole, the method further comprises forming a source/drain metal layer, which is filled with the source/drain contact hole and electrically connected to the source/drain.  
   
   
       12 . A thin film transistor, suitable for the use in a display, the thin film transistor comprising: 
 a substrate;    a poly-silicon island, disposed on the substrate, wherein the poly-silicon island comprises a source/drain and a channel between the source/drain;    a patterned gate dielectric layer, disposed above the channel of the poly-silicon island;    a gate, disposed on the patterned gate dielectric layer;    a silicide layer, formed above the source/drain of the poly-silicon island;    an inter-layer dielectric, which covers the substrate;    a source/drain contact, disposed in the inter-layer dielectric and the source/drain contact is electrically connected with the source/drain; and    a source/drain metal layer, disposed on the inter-layer dielectric, wherein the source/drain metal layer is electrically connected with the source/drain contact and electrically connected with the source/drain through the silicide layer.    
   
   
       13 . The thin film transistor as recited in  claim 12 , wherein the material of the silicide layer is selected from one of PdSi—TiSi—NiSi—TiWSi—WSi—CoSi—TaSi—MoSi—PtSi—GeSi and the combination thereof.  
   
   
       14 . The thin film transistor as recited in  claim 12 , further comprising a buffer layer disposed betweep the substrate and the poly-silicon island.  
   
   
       15 . The thin film transistor as recited in  claim 14 , wherein the material of the buffer layer comprises silicon nitrides.  
   
   
       16 . A pixel structure, suitable for the use in a display, the pixel structure comprising: 
 a substrate;    a poly-silicon island, disposed on the substrate, wherein the poly-silicon island comprises a source/drain and a channel between the source/drain;    a patterned gate dielectric layer, disposed above the channel of the poly-silicon island;    a gate, disposed on the patterned gate dielectric layer;    a silicide layer, formed above the source/drain of the poly-silicon island;    an inter-layer dielectric, which covers the substrate;    a source/drain contact, disposed in the inter-layer dielectric and the source/drain contact is electrically connected with the source/drain;    a source/drain metal layer, disposed on the inter-layer dielectric, wherein the source/drain metal layer is electrically connected with the source/drain contact and electrically connected with the source/drain through the silicide layer;    a patterned protecting layer, disposed on the substrate, wherein the patterned protecting layer comprises an opening to expose the source/drain metal layer; and    a pixel electrode, disposed on the patterned protecting layer, wherein the pixel electrode is filled in the opening to electrically connected with the source/drain metal layer.    
   
   
       17 . The pixel structure as recited in  claim 16 , wherein the material of the silicide layer is selected from one of PdSi—TiSi—NiSi—TiWSi—WSi—CoSi—TaSi—MoSi—PtSi—GeSi and the combination thereof.  
   
   
       18 . The pixel structure as recited in  claim 16 , further comprising a buffer layer, disposed between the substrate and the poly-silicon island.  
   
   
       19 . The pixel structure as recited in  claim 18 , wherein the material of the buffer layer comprises silicon nitrides.