US2007052040A1PendingUtilityA1

Transistor with contoured channel and method for making the same

Individually held — no corporate assignee on recordPriority: Dec 30, 2003Filed: Nov 6, 2006Published: Mar 8, 2007

Est. expiryDec 30, 2023(expired)· nominal 20-yr term from priority

Inventors:Ulrike Schwerin

H10D 30/62H10D 30/024H10B 12/053H10B 12/0335H10B 12/488H10B 12/056H10B 12/34H10B 12/485

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References

Claims

Abstract

A transistor structure such as a FinFET is formed in a semiconductor substrate with a surface contour having an upper surface at least partially bounded by sidewalls of trenches in the semiconductor substrate. First and second source/drain regions are arranged along the upper surface of the surface contour, with a recess structure between the first and second source/drain regions. The recess structure extends further into the semiconductor substrate than the first and second source/drain regions such that a channel within the semiconductor substrate between the first and second source/drain regions extends around the recess structure. The effective length of the channel is a function of the depth of the recess structure. A gate electrode is arranged along at least one of the sidewalls adjacent the channel. The effective channel width is a function of the depth to which the gate electrode is formed.

Claims

exact text as granted — not AI-modified

1 . A transistor structure, comprising:
a semiconductor substrate with a surface contour having an upper surface at least partially bounded by sidewalls of trenches formed in the semiconductor substrate; first and second source/drain regions arranged along the upper surface of the surface contour; a curved channel region extending through the semiconductor substrate between the first and second source/drain regions; a gate dielectric arranged along at least one of the sidewalls adjacent the channel region; and a gate electrode next to the gate dielectric.

2 . The transistor structure of claim 1 , wherein an effective channel length of the channel region is greater than a spacing between the first and second source/drain regions.

3 . The transistor structure of claim 1 , further comprising:
a recess structure between the first and second source/drain regions, the recess structure extending further into the semiconductor substrate than the first and second source/drain regions such that a contour of the channel region extends around the recess structure and the effective channel length is a function of a depth to which the recess structure extends into the semiconductor substrate.

4 . The transistor structure of claim 3 , wherein the gate electrode extends along the at least one of the sidewalls, adjacent the gate dielectric from at least lower edges of the first and second source/drain regions to beyond a lower edge of the recess structure.

5 . The transistor structure of claim 3 , wherein the recess structure is filled with at least one of silicon oxide and silicon nitride.

6 . The transistor structure of claim 1 , wherein the trenches include two substantially parallel trenches respectively defining first and second sidewalls, and wherein the gate electrode includes a first portion disposed along the first sidewall and a second portion disposed along the second sidewall such that the channel region lies between the first and second portions of the gate electrode.

7 . The transistor structure of claim 1 , wherein an effective channel width of the channel region is a function of a depth of the gate electrode along the at least one of the sidewalls in a direction extending into the semiconductor substrate.

8 . The transistor structure of claim 1 , wherein the first and second source/drain regions are source/drain regions.

9 . A memory cell, comprising:
a selection transistor comprising: a semiconductor substrate with a surface contour having an upper surface at least partially bounded by sidewalls of trenches formed in the semiconductor substrate; first and second source/drain regions arranged along the upper surface of the surface contour; a curved channel region extending through the semiconductor substrate between the first and second source/drain regions; a gate dielectric arranged along at least one of the sidewalls adjacent the channel region; and a gate electrode next to the gate dielectric; and a storage element connected to the selection transistor by an electrical path.

10 . The memory cell of claim 9 , wherein the first source/drain region is connected to the storage element, the second source/drain region is connected to a data line for supplying and conducting away electrical charge, and the gate electrode is connected to an addressing line for controlling the memory cell.

11 . The memory cell of claim 9 , wherein the storage element comprises a storage capacitor.

12 . The memory cell of claim 11 , wherein the storage capacitor comprises a stacked capacitor.

13 . A memory cell array comprising a plurality of memory cells, wherein individual ones of the memory cells comprise:
a selection transistor comprising: a semiconductor substrate with a surface contour having an upper surface at least partially bounded by sidewalls of trenches formed in the semiconductor substrate; first and second source/drain regions arranged along the upper surface of the surface contour; a curved channel region extending through the semiconductor substrate between the first and second source/drain regions; a gate dielectric arranged along at least one of the sidewalls adjacent the channel region; and a gate electrode next to the gate dielectric; and a storage element connected to the selection transistor by an electrical path.

14 . The memory cell array of claim 13 , wherein the memory cells are arranged in a chessboard pattern.

15 . The memory cell array of claim 13 , wherein the first gate electrodes of the selection transistors of the memory cells are arranged along a first trench and the second gate electrodes of the selection transistors of the memory cells are arranged along a second trench and the gates electrodes are coupled to a word line.

16 . A fin field effect transistor (FinFET), comprising:
first and second source/drain regions arranged along an upper surface of a semiconductor substrate fin structure; a recess structure between the first and second source/drain regions; dielectric layers arranged at least partially along the sidewalls of the semiconductor substrate fin structure adjacent the recess structure; and gate electrodes adjacent the dielectric material.

17 . The FinFET of claim 16 , wherein the recess structure extends further into the semiconductor substrate fin structure than the first and second source/drain regions, the FinFET further comprising a channel region extending between the first and second source/drain regions through the semiconductor substrate fin structure such that a contour of the channel region extends around the recess structure.

18 . The FinFET of claim 17 , wherein a length of the channel region is a function of a depth to which the recess structure extends into the semiconductor substrate fin structure.

19 . The FinFET of claim 16 , wherein the gate electrodes extend along the sidewalls from at least lower edges of the first and second source/drain regions to beyond a lower edge of the recess structure.

20 . A fin field effect transistor (FinFET), comprising:
first and second source/drain regions arranged along an upper surface of a semiconductor substrate fin structure; a channel region extending through the semiconductor substrate fin structure between the first and second source/drain regions, the channel region having a contour that diverges from the upper surface of the semiconductor substrate fin structure between the first and second source/drain regions; a gate electrode arranged along at least one sidewall of the semiconductor substrate fin structure adjacent the channel region; and a gate dielectric layer between the gate electrode and the channel region.

21 . The FinFET of claim 20 , wherein an effective channel length of the channel region is greater than a spacing between the first and second source/drain regions.

22 . The FinFET of claim 20 , further comprising:
a recess structure between the first and second source/drain regions, the recess structure extending further into the semiconductor substrate fin structure than the first and second source/drain regions such that a contour of the channel region extends around the recess structure and the effective channel length is a function of a depth to which the recess structure extends into the semiconductor substrate fin structure.

23 . The FinFET of claim 22 , wherein the gate electrode extends along the at least one sidewall from at least lower edges of the first and second source/drain regions to beyond a lower edge of the recess structure.

24 . The FinFET of claim 20 , wherein the gate electrode includes a first portion disposed along a first sidewall and a second portion disposed along a second sidewall on an opposite side of the semiconductor fin structure, such that the channel region lies between the first and second portions of the gate electrode.

25 . A multiple-gate field effect transistor (MUGFET), comprising:
first and second source/drain regions formed in a semiconductor substrate; a recessed channel region extending between the first and second source/drain regions; and first and second gate electrodes separated by the first and second source/drain regions and the recessed channel region.

26 . A transistor structure, comprising:
a source region and a drain region in a semiconductor substrate; a recessed channel region extending between the source and the drain region; and two gate electrodes separated by the source region, the drain region and the recessed channel region.

27 . The transistor structure of claim 26 , wherein an effective channel length of the channel region is greater than a spacing between the source and drain regions.

28 . The transistor structure of claim 26 , further comprising:
a recess structure between the source and drain regions, the recess structure extending further into the semiconductor substrate than the source and drain regions such that a contour of the channel region extends around the recess structure and the effective channel length is a function of a depth to which the recess structure extends into the semiconductor substrate.

29 . The transistor structure of claim 26 , wherein the transistor structure comprises a fin field effect transistor (FinFET).

30 . A transistor structure, comprising:
first and second means for conducting an electrical charge in respective surface regions of a semiconductor substrate; means for conveying the electrical charge through the semiconductor substrate between the first and second means for conducting; means for causing the means for conveying to have a curved contour; and means for activating the means for conveying.

31 . A method for fabricating a transistor structure, comprising:
forming trenches in a semiconductor substrate such that a surface contour of the semiconductor substrate has an upper surface at least partially bounded by sidewalls of trenches; forming first and second source/drain regions along the upper surface of the surface contour; forming a curved channel region extending through the semiconductor substrate between the first and second source/drain regions; forming a gate dielectric along at least one of the sidewalls adjacent the channel region; and forming a gate electrode adjacent the gate dielectric.

32 . The method of claim 31 , wherein the channel region is formed such that an effective channel length of the channel region is greater than a spacing between the first and second source/drain regions.

33 . The method of claim 31 , further comprising:
forming a recess structure between the first and second source/drain regions, the recess structure extending further into the semiconductor substrate than the first and second source/drain regions such that a contour of the channel region extends around the recess structure and the effective channel length is a function of a depth to which the recess structure extends into the semiconductor substrate.

34 . The method of claim 31 , wherein the gate electrode is formed to extend along the at least one of the sidewalls, adjacent the gate dielectric, from at least lower edges of the first and second source/drain regions to beyond a lower edge of the recess structure.

35 . The method of claim 31 , wherein the recess structure is filled with at least one of silicon oxide and silicon nitride.

36 . The method of claim 31 , wherein forming the trenches includes forming two substantially parallel trenches respectively defining first and second sidewalls, and wherein forming the gate electrode includes forming a first portion along the first sidewall and a second portion along the second sidewall such that the channel region lies between the first and second portions of the gate electrode.

37 . The method of claim 31 , wherein an effective channel width of the channel region is a function of a depth of the gate electrode along the at least one of the sidewalls in a direction extending into the semiconductor substrate.

38 . The method of claim 31 , wherein the transistor structure is formed as a fin field effect transistor (FinFET).

39 . A method for fabricating a memory cell, comprising:
forming a selection transistor by:
forming trenches in a semiconductor substrate such that a surface contour of the semiconductor substrate has an upper surface at least partially bounded by sidewalls of trenches;
forming first and second source/drain regions along the upper surface of the surface contour;
forming a curved channel region extending through the semiconductor substrate between the first and second source/drain regions;
forming a gate dielectric along at least one of the sidewalls adjacent the channel region; and
forming a gate electrode adjacent the gate dielectric; and
forming a storage element coupled to the selection transistor.

40 . The method of claim 39 , further comprising:
coupling the first source/drain region to the storage element; coupling the second source/drain region to a data line; and coupling the gate electrode to an addressing line.

41 . The method of claim 39 , wherein the storage element is formed as a storage capacitor.

42 . The method of claim 39 , wherein the storage capacitor is formed as a stacked capacitor.

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