US2007052028A1PendingUtilityA1
Semiconductor memory device including an SOI substrate
Est. expiryDec 3, 2013(expired)· nominal 20-yr term from priority
H10D 89/10H10D 86/201H10D 86/01H10B 12/50G11C 11/4097G11C 11/404H10B 12/00H10B 12/20G11C 2211/4016
52
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Claims
Abstract
A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.
Claims
exact text as granted — not AI-modified1 - 34 . (canceled)
35 . A semiconductor memory device comprising a plurality of MOS semiconductor elements,
wherein said plurality of MOS semiconductor elements are formed on an SOI substrate, wherein the source regions and the drain regions of said plurality of MOS semiconductor elements are in contact with an insulation layer in said SOI substrate.
36 - 43 . (canceled)Join the waitlist — get patent alerts
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