Non-contact etch annealing of strained layers

Abstract

The present invention provides a method of forming a strained semiconductor layer. The method comprises growing a strained first semiconductor layer, having a graded dopant profile, on a wafer, having a first lattice constant. The dopant imparts a second lattice constant to the first semiconductor layer. The method further comprises growing a strained boxed second semiconductor layer having the second lattice constant on the first semiconductor layer and growing a sacrificial third semiconductor layer having the first lattice constant on the second semiconductor layer. The method further comprises etch annealing the third and second semiconductor layer, wherein the third semiconductor layer is removed and the second semiconductor layer is relaxed. The method may further comprises growing a fourth semiconductor layer having the second lattice constant on the second semiconductor layer, wherein the fourth semiconductor layer is relaxed, and growing a strained fifth semiconductor layer having the first semiconductor lattice constant on the fourth semiconductor layer. The method controls the surface roughness of the semiconductor layers. The method also has the unexpected benefit of reducing dislocations in the semiconductor layers.

1 - 15 . (canceled)  
   
   
       16 . A method comprising: 
 forming over a strained semiconductor layer having a lattice constant, a second strained semiconductor layer also having the lattice constant;    forming a sacrificial semiconductor layer having a second lattice constant on said second semiconductor layer;    annealing the sacrificial semiconductor layer and the second strained semiconductor layer in an etching ambient to remove the sacrificial semiconductor layer and reduce strain in a second semiconductor layer;    forming a relaxed semiconductor layer having the lattice constant on the second semiconductor layer; and    forming a third strained semiconductor layer having the lattice constant on the relaxed semiconductor layer.    
   
   
       17 . The method of  claim 17  wherein at least one of the strained semiconductor layer, the second strained semiconductor layer, the sacrificial semiconductor layer, the relaxed semiconductor layer, and the third strained semiconductor layer are formed by epitaxial deposition of graded silicon germanium.  
   
   
       18 . The method of  claim 17  wherein the epitaxial deposition is performed in a hydrogen-chloride ambient.  
   
   
       19 . The method of  claim 16  further comprising: 
 providing a substrate having the second lattice constant; and    forming the strained semiconductor layer with a graded dopant profile on the substrate.    
   
   
       20 . The method of  claim 19  wherein the graded dopant profile imparts the lattice constant to the strained semiconductor layer.  
   
   
       21 . The method of  claim 16  wherein the etching ambient comprises a halogen bearing etchant.  
   
   
       22 . The method of  claim 21  wherein said halogen bearing etchant is hydrogen chloride.  
   
   
       23 . The method of  claim 21  wherein said halogen bearing etchant is hydrogen fluoride.  
   
   
       24 . The method of  claim 21  wherein etching ambient further comprises hydrogen.  
   
   
       25 . The method of  claim 21  wherein the annealing increases a temperature of the sacrificial semiconductor layer. to between about 700-1200° C.  
   
   
       26 . A method of controlling the surface roughness of a strained semiconductor material comprising: 
 forming a first strained semiconductor layer having a graded dopant profile on a wafer having a first lattice constant, the dopant imparting a second lattice constant to the first semiconductor layer;    forming a second strained semiconductor layer having said second lattice constant on the first semiconductor layer;    forming a sacrificial semiconductor layer having the first lattice constant on the second semiconductor layer; and    etch annealing the third and second semiconductor layer, wherein said third semiconductor layer is removed and said second semiconductor layer is relaxed.    
   
   
       27 . The method of  claim 26  wherein the etch annealing comprises exposing the third semiconductor layer to an etch ambient comprising a halogen bearing etchant.  
   
   
       28 . The method of  claim 27  wherein said halogen bearing etchant is hydrogen chloride.  
   
   
       29 . The method of  claim 27  wherein said halogen bearing etchant is hydrogen fluoride.  
   
   
       30 . The method of  claim 26  wherein etch annealing said surface of the third semiconductor layer further comprises exposing the third semiconductor layer to hydrogen.  
   
   
       31 . The method of  claim 26 , wherein etch annealing said third semiconductor layer further comprises increasing a temperature of said third semiconductor layer. to between 700 and 1200 degrees Celsius.  
   
   
       32 . The method of  claim 26  wherein at least one of the first strained semiconductor layer, the second strained semiconductor layer, and the sacrificial semiconductor layer are formed by epitaxial deposition of graded silicon germanium.  
   
   
       33 . The method of  claim 32  wherein the epitaxial deposition is performed in a hydrogen-chloride ambient.  
   
   
       34 . A method of reducing dislocations in a semiconductor material comprising relaxing a strained semiconductor layer having a first lattice constant by etch annealing to remove an overlying sacrificial semiconductor layer having a second lattice constant, the strained semiconductor layer formed over a second strained second semiconductor layer having a second lattice constant imparted by a graded dopant profile.  
   
   
       35 . The method of  claim 34  wherein the etch annealing comprises exposing the strained semiconductor layer and the sacrificial semiconductor layer to an etch ambient comprising a halogen bearing etchant.  
   
   
       36 . The method of  claim 34  wherein said halogen bearing etchant is hydrogen chloride.  
   
   
       37 . The method of  claim 34  wherein said halogen bearing etchant is hydrogen fluoride.  
   
   
       38 . The method of  claim 34  wherein the etch annealing further comprises exposing the strained semiconductor layer and the sacrificial semiconductor layer to hydrogen.