Vertical Twist Scheme for High Density DRAMs

Abstract

An interconnection array subunit and method for forming the interconnection array subunit are provided, the interconnection array subunit including a first pair of line conductors in first and second regions, the first pair of line conductors including a first true line conductor and a first associated complementary line conductor connected and vertically twisted in a vertical twisting region between the first and second regions. The interconnection array subunit also includes a second pair of line conductors adjacent to the first pair of line conductors in the first and second regions, the second pair of line conductors including a second true line conductor and a second associated complementary line conductor. The interconnection array subunit also includes a first interconnection layer disposed in the vertical twisting region, the first interconnection layer connecting the second associated complementary line conductor in the first region to the second associated complementary line conductor in the second region. The interconnection array subunit also includes a second interconnection layer disposed in the vertical twisting region, the second interconnection layer connecting the second true line conductor in the first region to the second true line conductor in the second region. The first true line conductor is disposed below the first associated complementary line conductor in the first region and above the first associated complementary line conductor in the second region. The second true line conductor is disposed below the second associated complementary line conductor in the first and second regions.

1 . A line conductor layout method for an interconnection array, the method comprising: 
 forming a plurality of first paired line conductors, each pair including a first true line conductor and a first associated complementary line conductor, the plurality of first paired line conductors being substantially parallel within a first region and within a second region, each of the first true line conductors being disposed below each of the first associated complementary line conductors in the first region and each of the first true line conductors being disposed above each of the first associated complementary line conductors in the second region;    forming a plurality of second paired line conductors, each pair including a second true line conductor and a second associated complementary line conductor, the plurality of second paired line conductors being substantially parallel within the first region and within the second region, each of the second true line conductors being disposed below each of the second associated complementary line conductors in the first region and in the second region, the plurality of second paired line conductors alternating with the plurality of first paired line conductors so that each pair of the plurality of first paired line conductors is adjacent to a corresponding pair of the plurality of second paired line conductors;    forming a plurality of first interconnection layers disposed in a vertical twisting region between the first region and the second region, each of the first interconnection layers connecting a respective second associated complementary line conductor of the plurality of second paired line conductors in the first region to a corresponding second associated complementary line conductor of the plurality of second paired line conductors in the second region, the plurality of first interconnection layers being disposed below first portions of the plurality of first paired line conductors in the vertical twisting region; and    forming a plurality of second interconnection layers disposed in the vertical twisting region, each of the second interconnection layers connecting a respective second true line conductor of the plurality of second paired line conductors in the first region to a corresponding second true line conductor of the plurality of second paired line conductors in the second region;    wherein the plurality of second interconnection layers alternate with the plurality of first interconnection layers such that each of the first interconnection layers of the plurality of first interconnection layers is non-overlapping with a corresponding second interconnection layer of the plurality of second interconnection layers;    and wherein the plurality of second interconnection layers is disposed below second portions of the plurality of first paired line conductors in the vertical twisting region;    and wherein each of the first true line conductors of the plurality of first paired line conductors in the first region is connected in the vertical twisting region to a respective first true line conductor of the plurality of first paired line conductors in the second region and each of the first associated complementary line conductors of the plurality of first paired line conductors in the first region is connected in the vertical twisting region to a respective first associated complementary line conductor of the plurality of first paired line conductors in the second region.    
   
   
       2 . The method of  claim 1 , wherein the first and second true line conductors include polycide.  
   
   
       3 . The method of  claim 1 , wherein the first and second associated complementary line conductors include metal.  
   
   
       4 . The method of  claim 1 , wherein the first interconnection layers include polysilicon.  
   
   
       5 . The method of  claim 1 , wherein the second interconnection layers are formed to include active areas.  
   
   
       6 . The method of  claim 1 , wherein a first pitch between successive first paired line conductors and second paired line conductors in the first region is formed to be substantially similar to a second pitch between successive first paired line conductors and second paired line conductors in the second region.  
   
   
       7 . The method of  claim 1 , wherein each of the first interconnection layers is connected to the respective and corresponding second associated complementary line conductors through respective first and second contact holes disposed substantially at respective first and second peripheral portions of each of the first interconnection layers in the vertical twisting region.  
   
   
       8 . The method of  claim 1 , wherein each of the second interconnection layers is connected to the respective and corresponding second true line conductors through respective first and second overlapping interconnects disposed substantially at respective first and second peripheral portions of each of the second interconnection layers in the vertical twisting region.  
   
   
       9 . The method of  claim 1 , wherein each of the first true line conductors of the plurality of first paired line conductors in the first region is connected to the respective first true line conductor of the plurality of first paired line conductors in the second region through a third contact hole in the vertical twisting region.  
   
   
       10 . The method of  claim 1 , wherein each of the first associated complementary line conductors of the plurality of first paired line conductors in the first region is connected to the respective first associated complementary line conductor of the plurality of first paired line conductors in the second region through a fourth contact hole in the vertical twisting region.  
   
   
       11 . The method of  claim 2 , wherein: 
 the first and second associated complementary line conductors are formed to include metal;    the first interconnection layers are formed to include polysilicon and the second interconnection layers are formed to include active areas;    a first pitch between successive first paired line conductors and second paired line conductors in the first region is formed to be substantially similar to a second pitch between successive first paired line conductors and second paired line conductors in the second region;    each of the first interconnection layers is connected to the respective and corresponding second associated complementary line conductors through respective first and second contact holes disposed substantially at respective first and second peripheral portions of each of the first interconnection layers in the vertical twisting region;    each of the first true line conductors of the plurality of first paired line conductors in the first region is connected to the respective first true line conductor of the plurality of first paired line conductors in the second region through a third contact hole in the vertical twisting region;    each of the first associated complementary line conductors of the plurality of first paired line conductors in the first region is connected to the respective first associated complementary line conductor of the plurality of first paired line conductors in the second region through a fourth contact hole in the vertical twisting region;    and each of the second interconnection layers is connected to the respective and corresponding second true line conductors through respective first and second overlapping interconnects disposed substantially at respective first and second peripheral portions of each of the second interconnection layers in the vertical twisting region.    
   
   
       12 . A line conductor layout method for an interconnection array subunit, the method comprising: 
 forming a first pair of line conductors in first and second regions, the first pair of line conductors including a first true line conductor and a first associated complementary line conductor connected and vertically twisted in a vertical twisting region between the first and second regions;    forming a second pair of line conductors adjacent to the first pair of line conductors in the first and second regions, the second pair of line conductors including a second true line conductor and a second associated complementary line conductor;    forming a first interconnection layer disposed in the vertical twisting region, the first interconnection layer connecting the second associated complementary line conductor in the first region to the second associated complementary line conductor in the second region; and    forming a second interconnection layer disposed in the vertical twisting region, the second interconnection layers connecting the second true line conductor in the first region to the second true line conductor in the second region, wherein the first true line conductor is disposed below the first associated complementary line conductor in the first region and above the first associated complementary line conductor in the second region and the second true line conductor is disposed below the second associated complementary line conductor in the first and second regions.    
   
   
       13 . The method of  claim 12 , wherein the first interconnection layer is disposed below first portions of the first pair of line conductors in the vertical twisting region, the second interconnection layer is disposed below second portions of the first paired line conductors in the vertical twisting region.  
   
   
       14 . The method of  claim 13 , wherein the first interconnection layer is non-overlapping with the second interconnection layer.  
   
   
       15 . The method of  claim 14 , wherein the first and second true line conductors include polycide.  
   
   
       16 . The method of  claim 14 , wherein the first and second associated complementary line conductors include metal.  
   
   
       17 . The method of  claim 14 , wherein the first interconnection layer includes polysilicon.  
   
   
       18 . The method of  claim 14 , wherein the second interconnection layer includes active areas.  
   
   
       19 . The method of  claim 14 , wherein a first pitch between the first pair of line conductors and the second pair of line conductors in the first region is substantially similar to a second pitch between the first pair of line conductors and the second pair of line conductors in the second region.  
   
   
       20 . The method of  claim 14 , wherein: 
 the first interconnection layer connects to the second associated complementary line conductor through first and second contact holes disposed substantially at respective first and second peripheral portions of the first interconnection layer in the vertical twisting region;    the first true line conductor in the first region connects to the first true line conductor in the second region through a third contact hole in the vertical twisting region;    and the first associated complementary line conductor in the first region connects to the first associated complementary line conductor in the second region through a fourth contact hole in the vertical twisting region.    
   
   
       21 . The method of  claim 14 , wherein the second interconnection layer connects to the second true line conductor through first and second overlapping interconnects disposed substantially at respective first and second peripheral portions of the second interconnection layer in the vertical twisting region.  
   
   
       22 . The method of  claim 12 , wherein: 
 the first and second associated complementary line conductors include metal;    the first interconnection layer includes polysilicon and the second interconnection layer includes active areas;    a first pitch between the first pair of line conductors and the second pair of line conductors in the first region is substantially similar to a second pitch between the first pair of line conductors and the second pair of line conductors in the second region;    the first interconnection layer connects to the second associated complementary line conductor through first and second contact holes disposed substantially at respective first and second peripheral portions of the first interconnection layer in the vertical twisting region;    the first true line conductor in the first region connects to the first true line conductor in the second region through a third contact hole in the vertical twisting region;    the first associated complementary line conductor in the first region connects to the first associated complementary line conductor in the second region through a fourth contact hole in the vertical twisting region;    and the second interconnection layer connects to the second true line conductor through first and second overlapping interconnects disposed substantially at respective first and second peripheral portions of the second interconnection layer in the vertical twisting region.    
   
   
       23 . A method for forming an interconnection array in an integrated circuit, comprising: 
 forming a first twisting region;    forming a first pair of true and complementary conductive paths spanning from a left side of the first twisting region to a right side of the first twisting region; and    forming a second pair of true and complementary conductive paths spanning from a left side of the first twisting region to a right side of the first twisting region;    wherein the first twisting region affects a vertical twist in the first pair of conductive paths between the left side to the right side,    wherein the first twisting region does not affect a horizontal twist of the second pair of conductive paths between the left side to the right side, and    wherein the first twisting region does not affect a vertical twist in the second pair of conductive paths between the left side to the right side, although the first twisting region routes both of the conductive paths of the second pair to different layers in the integrated circuit using contacts or vias.    
   
   
       24 . The method of  claim 23 , wherein the first twisting region affects a vertical twist in the first pair of conductive paths by routing the conductive paths to different layers in the integrated circuit using contacts or vias.  
   
   
       25 . The method of  claim 23 , wherein the true and complementary conductive paths of the first pair are vertically spaced from each other on the right and left sides, and wherein the true and complementary conductive paths of the second pair are vertically spaced from each other on the right and left sides.  
   
   
       26 . The method of  claim 23 , wherein the first pair of conductive paths is horizontally adjacent the second pair of conductive paths.  
   
   
       27 . The method of  claim 23 , further comprising: 
 forming a second twisting region, wherein the second twisting region is horizontally displaced from the first twisting region along an axis generally parallel to an axis of the conductive path pairs;    wherein the second twisting region affects a vertical twist in the second pair of conductive paths between the left side to the right side,    wherein the second twisting region does not affect a horizontal twist of the first pair of conductive paths between the left side to the right side, and    wherein the second twisting region does not affect a vertical twist in the first pair of conductive paths between the left side to the right side, although the second twisting region routes both of the conductive paths of the first pair to different layers in the integrated circuit using contacts or vias.    
   
   
       28 . The method of  claim 23 , wherein the true conductive paths comprise a first conductive layer in the left and right sides.  
   
   
       29 . The method of  claim 28 , wherein the first conductive layer comprises polycide.  
   
   
       30 . The method of  claim 28 , wherein the complementary conductive paths comprise a second conductive layer in the left and right sides, wherein the second conductive layer is above the first conductive layer.  
   
   
       31 . The method of  claim 30 , wherein the complementary conductive paths comprise a metal.  
   
   
       32 . The method of  claim 30 , wherein second complementary conductive path comprises polysilicon in the twisting region.  
   
   
       33 . The method of  claim 32 , wherein the second true conductive path comprises an active area layer formed in a semiconductive substrate in the twisting region.  
   
   
       34 . A method for forming an interconnection array in an integrated circuit, comprising: 
 a first twisting region having left and right sides adjacent thereto;    a first pair of true and complementary conductive paths present in the first twisting region, in the left side, and in the right side; and    a second pair of true and complementary conductive paths present in the first twisting region, in the left side, and in the right side;    wherein the first twisting region affects a vertical twist in the first pair of conductive paths between the left side to the right side,    wherein the first twisting region does not affect a horizontal twist of the second pair of conductive paths between the left side to the right side, and    wherein the first twisting region does not affect a vertical twist in the second pair of conductive paths between the left side to the right side, although the first twisting region routes both of the conductive paths of the second pair to different layers in the integrated circuit using contacts or vias.    
   
   
       35 . The method of  claim 34 , wherein the first pair of conductive paths are formed along an first axis in the left side and in the right side, and wherein the second pair of conductive paths are formed along a second axis in the left side and in the right side.  
   
   
       36 . The method of  claim 35 , wherein the first twisting region affects a vertical twist in the first pair of conductive paths by routing the conductive paths to different layers in the integrated circuit using contacts or vias.  
   
   
       37 . The method of  claim 35 , wherein the true and complementary conductive paths of the first pair are vertically spaced from each other on the right and left sides, and wherein the true and complementary conductive paths of the second pair are vertically spaced from each other on the right and left sides.  
   
   
       38 . The method of  claim 35 , wherein the first pair of conductive paths is horizontally adjacent the second pair of conductive paths.  
   
   
       39 . The method of  claim 35 , further comprising: 
 forming a second twisting region having left and right sides adjacent thereto, wherein the second twisting region is horizontally displaced along an axis generally parallel to the first or second axes;    wherein the second twisting region affects a vertical twist in the second pair of conductive paths between the left side to the right side, and    wherein the second twisting region does not affect a horizontal twist of the first pair of conductive paths between the left side to the right side, and    wherein the second twisting region does not affect a vertical twist in the first pair of conductive paths between the left side to the right side, although the second twisting region routes both of the conductive paths of the first pair to different layers in the integrated circuit using contacts or vias.    
   
   
       40 . The method of  claim 34 , wherein the true conductive paths comprise a first conductive layer in the left and right sides.  
   
   
       41 . The method of  claim 40 , wherein the first conductive layer comprises polycide.  
   
   
       42 . The method of  claim 40 , wherein the complementary conductive paths comprise a second conductive layer in the left and right sides, wherein the second conductive layer is above the first conductive layer.  
   
   
       43 . The method of  claim 42 , wherein the complementary conductive paths comprise a metal.  
   
   
       44 . The method of  claim 42 , wherein second complementary conductive path comprises polysilicon in the twisting region.  
   
   
       45 . The method of  claim 44 , wherein the second true conductive path comprises an active area layer formed in a semiconductive substrate in the twisting region.