Error correction apparatus for performing consecutive reading of multiple code words

Abstract

An error correction apparatus for performing an error correction process on digital data that is stored in a buffer memory and includes multiple code words. The device includes a memory access circuit for controlling reading and writing of the code words to the buffer memory. Operational circuits perform a syndrome calculation with each of the multiple code words read from the buffer memory. The memory access circuit consecutively reads the multiple code words from the buffer memory and distributes the code words to the operational circuits.

1 . An error correction apparatus for performing an error correction process on digital data that is stored in a buffer memory and includes multiple code words, the apparatus comprising: 
 a memory access circuit for controlling reading and writing of the code words to the buffer memory, wherein the memory access circuit writes the processed data to the buffer memory;    a symbol counter for counting the number of symbols of the code words read from the buffer memory and generating a count value of a plurality of bits;    an error correction circuit for performing an error correction process on the multiple code words read from the buffer memory based on the syndrome calculate results by the plurality of operational circuits; and    an error detection circuit for checking whether error correction is properly performed on the error correction circuit,    wherein the memory access circuit consecutively reads the multiple code words from the buffer memory and distributes the read code words to the plurality operational circuits based on the count value of the lower bits of the plurality of bits, and wherein the number of lower bits is determined in accordance with the number of operational circuits.    
     
     
         2 . The apparatus according to  claim 1 , wherein each of the code words is formed by multiple symbols, and the memory access circuit reads the symbols of the code words.  
     
     
         3 . The apparatus according to  claim 2 , wherein the symbol counter includes: 
 a register for holding the count value;    a decoder for distributing the symbols read from the buffer memory to the plurality of the operational circuits in accordance with a timing for reading the symbols.    
     
     
         4 . The apparatus according to  claim 3 , wherein the count control circuit changes an adding condition of the count value when the count value exceeds a predetermined value.  
     
     
         5 . The apparatus according to  claim 1 , wherein the memory access circuit holds a row address of the buffer memory and changes a column address for each code word to consecutively read the multiple code words from the buffer memory.  
     
     
         6 . An error correction apparatus for performing an error correction process on digital data that is stored in a buffer memory and includes multiple code words, the apparatus comprising: 
 a memory access circuit connected to be buffer memory for reading and writing the code words to the buffer memory in accordance with an address signal;    an address generation circuit for generating the address signal to designate an address of the code words read from and written to the buffer memory and for providing the address signal to the memory access circuit;    a timing generation circuit connected to the address generation circuit for generating a timing signal to control the address generation circuit so that the address signal is generated to read the code words from the buffer memory;    a symbol counter for counting the number of symbols of the code words read from the buffer memory and generating a count value of a plurality of bits;    a syndrome generation circuit for generating multiple syndromes in parallel in correspondence with the multiple code words by processing the code words of the digital data read from the buffer memory based on the count value of the lower bits of the plurality of bits, wherein the number of lower bits is determined in accordance with the number of operational circuits;    an error correction circuit for performing an error correction process on the multiple code words read from the buffer memory based on the multiple syndromes generated by the syndrome generation circuit; and    an error detection circuit for checking whether error correction is properly performed on the error correction circuit.    
     
     
         7 . The apparatus according the  claim 6 , wherein the address signal includes a row address signal and a column address signal, and the control circuit controls the address generation circuit so that a plurality of the column address signals corresponding to the multiple code words are consecutively generated after the row address signal is generated.  
     
     
         8 . The apparatus according to  claim 6 , further comprising: 
 a detection circuit for detecting a page boundary signal by detecting a page boundary of the digital data based on the address signal generated by the address generation circuit.    
     
     
         9 . The apparatus according to  claim 8 , wherein the timing generation circuit generates the timing signal to control the address generation circuit so that the address signal changes in accordance with the page boundary signal.  
     
     
         10 . The apparatus according to  claim 6 , wherein the syndrome generation circuit includes a plurality of operational circuits for generating the syndromes in parallel.  
     
     
         11 . A method for performing an error correction process on digital data that is stored in a buffer memory and includes multiple code words, the method comprising the steps of: 
 consecutively reading the code words of the digital data from the buffer memory;    counting the number of symbols of the code words read from the buffer memory to generate a count value of a plurality of bits;    distributing the read code words to a plurality of operational circuits based on the count value of the lower bits of the plurality of bits, wherein the number of lower bits is determined in accordance with the number of operational circuits;    generating multiple syndromes in parallel by processing the code words of the digital data read from the buffer memory using the plurality of operational circuits;    performing the error correction process on the code words of the digital data read from the buffer memory using the multiple syndrome; and    performing an error detection process for checking whether error correction is properly performed in the error correction process.    
     
     
         12 . A method for performing an error correction process on digital data that is stored in a buffer memory and includes multiple code words, the method comprising the steps of: 
 consecutively generating an address signal to read the code words of the digital data from the buffer memory;    consecutively reading the code words of the digital data from the buffer memory in accordance with the address signal;    counting the number of symbols of the code words read from the buffer memory to generate a count value of a plurality of bits;    distributing the read code words to a plurality of operational circuits based on the count value of the lower bits of the plurality of bits, wherein the number of lower bits is determined in accordance with the number of operational circuits;    generating multiple syndromes in parallel by processing the code words of the digital data read from the buffer memory using the plurality of operational circuits; and    performing the error correction process on the code words of the digital data read from the buffer memory using the multiple syndromes.    
     
     
         13 . The method according to  claim 12 , wherein the address signal includes a row address signal and a column address signal, and the step for generating an address signal includes generating a row address signal and then consecutively generating a plurality of the column address signals corresponding to the multiple code words.  
     
     
         14 . The method according to  claim 12 , further comprising the step of; 
 generating a page boundary signal by detecting a page boundary of the digital data based on the address signal.    
     
     
         15 . The method according to  claim 14 , further comprising the step of: 
 changing the address signal in accordance with the page boundary signal.