Flash memory with low tunnel barrier interpoly insulators

Abstract

Structures and methods for Flash memory with low tunnel barrier intergate insulators are provided. The non-volatile memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , and Nb 2 O 5 . The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

1 . A method for forming an array of flash memory cells, comprising: 
 forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region;    forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;    forming a number of control gates opposing the floating gates;    forming a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;    forming a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gates lines are separated from the floating gates by a low tunnel barrier intergate insulator; and    forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of flash cells.    
   
   
       2 . The method of  claim 1 , wherein forming the low tunnel barrier intergate insulator includes forming a metal oxide insulator selected from the group consisting of PbO, Al 2 O 3 , TiO 2 , ZrO 2 , and Nb 2 O 5 .  
   
   
       3 . The method of  claim 1 , wherein forming each floating gate includes forming a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.  
   
   
       4 . The method of  claim 1 , wherein forming each control gate includes forming a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.  
   
   
       5 . The method of  claim 1 , wherein forming each floating gate includes forming a vertical floating gate in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.  
   
   
       6 . The method of  claim 5 , wherein forming the plurality of control gate lines includes forming each control gate line in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.  
   
   
       7 . The method of  claim 5 , wherein forming the plurality of control gate lines includes forming a pair of control gate lines in each trench below the top surface of the pillar and between the pair of floating gates such that each control gate line addresses a floating gate on opposing sides of the trench respectively, and wherein the pair of control gate lines are separated by an insulator layer.  
   
   
       8 . The method of  claim 5 , wherein forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates such that each pair of floating gates shares a single control gate line.  
   
   
       9 . The method of  claim 5 , wherein forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates, and forming the plurality of control lines such that each one of the pair of floating gates is addressed by an independent one of the plurality of control lines.  
   
   
       10 . The method of  claim 1 , wherein forming each floating gate includes forming a horizontally oriented floating gate in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposite sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.  
   
   
       11 . The method of  claim 10 , wherein the forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates.  
   
   
       12 . A method for forming an array of non-volatile memory cells, comprising: 
 forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region;    forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;    forming a number of control gates opposing the floating gates;    forming a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;    forming a low tunnel barrier, Ta 2 O 5  intergate insulator;    forming a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gates lines are separated from the floating gates by the low tunnel barrier intergate insulator; and    forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of flash cells.    
   
   
       13 . The method of  claim 12 , wherein forming each floating gate includes forming a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.  
   
   
       14 . The method of  claim 12 , wherein forming each control gate includes forming a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.  
   
   
       15 . The method of  claim 12 , wherein forming each floating gate includes forming a vertical floating gate in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.  
   
   
       16 . The method of  claim 15 , wherein forming the plurality of control gate lines includes forming each control gate line in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.  
   
   
       17 . The method of  claim 15 , wherein forming the plurality of control gate lines includes forming a pair of control gate lines in each trench below the top surface of the pillar and between the pair of floating gates such that each control gate line addresses a floating gate on opposing sides of the trench respectively, and wherein the pair of control gate lines are separated by an insulator layer.  
   
   
       18 . The method of  claim 15 , wherein forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates such that each pair of floating gates shares a single control gate line.  
   
   
       19 . The method of  claim 15 , wherein forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates, and forming the plurality of control lines such that each one of the pair of floating gates is addressed by an independent one of the plurality of control lines.  
   
   
       20 . The method of  claim 12 , wherein forming each floating gate includes forming a horizontally oriented floating gate in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposite sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.  
   
   
       21 . The method of  claim 20 , wherein the forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates.  
   
   
       22 . A method for forming an array of flash memory cells, comprising: 
 forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region;    forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide, wherein forming each floating gate includes forming a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator;    forming a number of control gates opposing the floating gates, wherein forming each control gate includes forming a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator;    forming a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;    forming a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gates lines are separated from the floating gates by a low tunnel barrier intergate insulator; and    forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of flash cells.    
   
   
       23 . The method of  claim 22 , wherein forming the low tunnel barrier intergate insulator includes forming a metal oxide insulator selected from the group consisting of PbO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , and Nb 2 O 5 .  
   
   
       24 . The method of  claim 23 , wherein forming each floating gate includes forming a vertical floating gate in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.