Continuously adjustable bandwidth discrete-time phase-locked loop

Abstract

A user equipment which receives a CDMA communication signal that is wirelessly transmitted includes a system for correcting phase errors in an information signal which has been transmitted. The correction system comprises circuitry for generating a correction signal and for combining the correction signal with the information signal to produce a corrected information signal. An analyzer analyzes the phase of the corrected information signal and generates an error signal based on the deviation of the analyzed phase from a reference phase. A bandwidth controller recursively adjusts the phase of the corrected information signal such that the phase of said corrected information signal is substantially equal to said reference phase. The bandwidth controller selects a bandwidth within an adjustable range based on the error signal, estimates an offset based on the error signal, and modifies the correction signal using the offset.

1 . A continuously adjusted-bandwidth phase-locked loop (PLL) for use in a CDMA receiver for correcting for deviation, or offset, that exists between a received radio frequency (RF) carrier signal and a frequency of a first stage local oscillator (LO), the PLL comprising: 
 a rake receiver for providing a despread pilot signal;    a mixer for mixing the despread pilot signal with a correction signal to produce a complex error signal;    a normalizing unit;    an arctangent analyzer for analyzing a signal provided by the normalizer to the determine a phase of the despread pilot signal and output a phase error signal;    a PLL filter;    voltage controlled oscillator for generating a local correction signal; and    a bandwidth controller for adjusting the bandwidth of the PLL filter to provide a revised correction signal to the mixer.    
   
   
       2 . The PLL of  claim 1  wherein the despread pilot signal is a complex number represented in Cartesian form.  
   
   
       3 . The PLL of  claim 1  wherein the despread pilot signal is a complex number represented in polar form including a magnitude and a phase angle.  
   
   
       4 . The PLL of  claim 1  wherein the arctangent analyzer and the normalizing unit are combined into a microprocessor.  
   
   
       5 . The PLL of  claim 1  wherein the arctangent analyzer uses a look-up table to determine the phase.  
   
   
       6 . The PLL of  claim 5  wherein the look-up table comprises a matrix of at least eight discrete in-phase component values by at least eight discrete quadrature component values.  
   
   
       7 . The PLL of  claim 1  wherein the normalizing unit receives a complex error signal from the mixer and performs a pseudo-normalization by dividing the complex error signal by either the imaginary or real component of the imaginary number.  
   
   
       8 . The PLL of  claim 1  wherein the normalizer performs true normalization, determines the magnitude of the complex error signal and divides the error signal by the magnitude.  
   
   
       9 . The PLL of  claim 1  wherein the bandwidth control unit comprises: 
 a squaring unit;    a leaky integrator unit;    a bandwidth calculation unit; and    a sample/hold unit.    
   
   
       10 . The PLL of  claim 1  wherein the bandwidth controller estimates an offset based on the phase error signal and determines the bandwidth adjustments based on the estimated offset.  
   
   
       11 . The PLL of  claim 1  wherein the voltage controlled oscillator implements bandwidth adjustments.