Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices

Abstract

Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.

1 . An integrated circuit controlled by one or more of a supply voltage and a reference voltage, comprising: 
 an independently controlled asymmetrical double-gate device to adjust one or more of said supply voltage and said reference voltage.    
   
   
       2 . The integrated circuit of  claim 1 , wherein said independent control comprises a back gate bias.  
   
   
       3 . The integrated circuit of  claim 1 , wherein said asymmetrical double-gate device is a pMOS device comprising: 
 a p+ polysilicon gate for a first gate; and    an n+ polysilicon gate for a second gate, wherein a threshold voltage, V T , is independently controlled by a bias of said first or second gates.    
   
   
       4 . The integrated circuit of  claim 1 , wherein said reference voltage is a ground voltage.  
   
   
       5 . The integrated circuit of  claim 1 , wherein said integrated circuit is a CMOS circuit.  
   
   
       6 . The integrated circuit of  claim 1 , wherein said independently controlled asymmetrical double-gate device employs a second gate to control a diode voltage.  
   
   
       7 . An integrated circuit controlled by one or more of a supply voltage and a reference voltage, comprising: 
 a back-gate controlled fully depleted Silicon-On-Insulator (SOI) device to adjust one or more of said supply voltage and said reference voltage.    
   
   
       8 . An integrated circuit comprising: 
 a plurality of voltage islands each providing a different voltage level, each voltage island comprising:    an independently controlled asymmetrical double-gate device to provide one of said different voltage levels.    
   
   
       9 . The integrated of  claim 8 , wherein each of said of said different voltage levels are obtained using a corresponding back-gate bias.  
   
   
       10 . A power gating circuit, comprising: 
 at least one integrated circuit; and    an independently controlled asymmetrical double-gate device that provides a variable threshold voltage, V T .    
   
   
       11 . The power gating circuit of  claim 10 , further comprising an asymmetrical double-gate device to serve as a power switch.  
   
   
       12 . The power gating circuit of  claim 11 , wherein in an active mode, said power switch is ON and said independently controlled asymmetrical double-gate device is ON.  
   
   
       13 . The power gating circuit of  claim 11 , wherein in a standby mode, said power switch is OFF, and said independently controlled asymmetrical double-gate device is biased to provide a diode voltage to clamp virtual GND and virtual V DD  at predefined levels.  
   
   
       14 . A static RAM device, comprising: 
 a plurality of memory cells, each having an independently controlled asymmetrical double-gate device that provides a variable threshold voltage, V T .    
   
   
       15 . The static RAM device of  claim 14 , wherein said independently controlled asymmetrical double-gate devices serve as a power switch and a variable diode-voltage clamp.  
   
   
       16 . The static RAM device of  claim 14 , wherein in a standby mode, diode voltages of said independently controlled asymmetrical double-gate devices can be tuned to compensate for one or more process variations or V T  fluctuation and to reduce leakage currents.  
   
   
       17 . The static RAM device of  claim 14 , wherein a back-gate bias on said independently controlled asymmetrical double-gate devices is used to control a voltage across said plurality of cells.  
   
   
       18 . A processor unit, comprising: 
 an oscillator;    at least one independently controlled asymmetrical double-gate device that provides a variable threshold voltage, V T ;    a phase detector to compare an output of said oscillator to a reference signal; and    a charge pump to adjust a back-gate bias of said at least one independently controlled asymmetrical double-gate device based on said comparison.    
   
   
       19 . The processor unit of  claim 18 , wherein said adjusted back-gate bias improves a power performance of said processing unit.  
   
   
       20 . The processor unit of  claim 18 , wherein said adjusted back-gate bias maintains a required performance with a reduced supply voltage.