Semiconductor device

Abstract

The present invention provides a technique capable of simplifying a layout structure of a semiconductor device having a semiconductor memory section in which an input port and an output port are separated from each other, and which includes a bypass function. In a semiconductor memory device to be used as a semiconductor memory section of the semiconductor device, in a bypass mode, an output buffer outputs input data transmitted through a bypass line, extending from an input buffer circuit to the output buffer circuit, to an output port. In the layout structure of the semiconductor memory device, in plan view, a memory cell array is arranged between the input buffer circuit and the output buffer circuit, and a bypass line is arranged through between the memory cell arrays.

1 . A semiconductor device comprising a semiconductor memory section that has a write mode, a read mode and a bypass mode, wherein 
 said semiconductor memory section includes:    first and second memory cell arrays each having a plurality of memory cells arranged in a predetermined direction;    first and second input ports which are respectively provided corresponding to said first and second memory cell arrays and into which data are inputted;    first and second output ports which are respectively provided corresponding to said first and second memory cell arrays and from which data are outputted;    a plurality of read word lines respectively connected to said plurality of memory cells in each of said first and second memory cell arrays;    a plurality of write word lines respectively connected to said plurality of memory cells in each of said first and second memory cell arrays;    a decoder circuit which activates any one of said plurality of write word lines in said write mode, and activates any one of said plurality of read word lines in said read mode;    first and second input buffer circuits which respectively receive data having been inputted into said first and second input ports, and output the received data;    a first write bit line which extends from said first input buffer circuit to said first memory cell array, and transmits data outputted from said first input buffer circuit to said first memory cell array;    a second write bit line which extends from said second input buffer circuit to said second memory cell array, and transmits data outputted from said second input buffer circuit to said second memory cell array;    first and second output buffer circuits which respectively output the received data to said first and second output ports;    a first read bit line which extends from said first memory cell array to said first output buffer circuit, and transmits data from said first memory cell array to said first output buffer circuit;    a second read bit line which extends from said second memory cell array to said second output buffer circuit, and transmits data from said second memory cell array to said second output buffer circuit;    a first bypass line which extends from said first input buffer circuit to said first output buffer circuit, and transmits data, having been inputted into said first input buffer circuit from said first input port, to said first output buffer circuit; and    a second bypass line which extends from said second input buffer circuit to said second output buffer circuit, and transmits data, having been inputted into said second input buffer circuit from said second input port, to said second output buffer circuit,    said first output buffer circuit outputs data transmitted through said first read bit line to said first output port in said read mode, and outputs data transmitted through said first bypass line to said first output port in said bypass mode,    said second output buffer circuit outputs data transmitted through said second read bit line to said second output port in said read mode, and outputs data transmitted through said second bypass line to said second output port in said bypass mode, and    in the layout structure in plan view,    said first memory cell array is arranged between said first input buffer circuit and said first output buffer circuit,    said second memory cell array is arranged between said second input buffer circuit and said second output buffer circuit, and    said first bypass line is arranged through between said first and second memory cell arrays.    
   
   
       2 . The semiconductor device according to  claim 1 , further comprising a plurality of wiring layers which are laminated to each other, wherein 
 in the layout structure,    in plan view, said first write bit line and said first read bit line are arranged on a region where said plurality of memory cells are formed in said first memory cell array, and said second write bit line and said second read bit line are arranged on a region where said plurality of memory cells are formed in said second memory cell array, and    said first and second bypass lines, said first and second write bit lines and said first and second read bit lines are arranged in the same wiring layer.    
   
   
       3 . A semiconductor device comprising a semiconductor memory section that has a write mode, a read mode and a bypass mode, wherein 
 said semiconductor memory section includes:    a memory cell array having a plurality of memory cells arranged. in a predetermined direction;    an input port into which data is inputted;    an output port from which data is outputted;    a plurality of read word lines respectively connected to said plurality of memory cells in said memory cell array;    a plurality of write word lines respectively connected to said plurality of memory cells in said memory cell array;    a decoder circuit which activates any one of said plurality of write word lines in said write mode, and activates any one of said plurality of read word lines in said read mode;    an input buffer circuit which receives data having been inputted into said input port, and outputs the received data;    a write bit line which extends from said input buffer circuit to said memory cell array, and transmits data outputted from said input buffer circuit to said memory cell array;    an output buffer circuit which outputs the received data to said output port;    a read bit line which extends from said memory cell array to said output buffer circuit, and transmits data from said memory cell array to said output buffer circuit;    a bypass line which extends from said input buffer circuit to said output buffer circuit, and transmits data, having been inputted into said input buffer circuit from said input port, to said output buffer circuit;    power wiring which gives a power potential to said memory cell array; and    ground wiring which gives a ground potential to said memory cell array,    said output buffer circuit outputs data transmitted through said read bit line to said output port in said read mode, and outputs data transmitted through said bypass line to said output port in said bypass mode, and    in the layout structure in plan view,    said memory cell array is arranged between said input buffer circuit and said output buffer circuit, and    said bypass line, said write bit line, said read bit line, said power wiring and said ground wiring are arranged on a region where said plurality of memory cells are formed in said memory cell array.    
   
   
       4 . The semiconductor device according to  claim 3 , further comprising a plurality of wiring layers which are laminated to each other, wherein 
 in the layout structure, said bypass line, said write bit line, said read bit line, said power wiring and said ground wiring are arranged in the same wiring layer.    
   
   
       5 . The semiconductor device according to  claim 3 , further comprising a plurality of wiring layers which are laminated to each other, wherein 
 in the layout structure,    said write bit line, said read bit line, said power wiring and said ground wiring are arranged in the same wiring layer, and    said bypass line is arranged in a wiring layer different from the wiring layer for said power wiring and said ground wiring, so as to overlap with said power wiring or said ground wiring in plan view.    
   
   
       6 . The semiconductor device according to  claim 1 , wherein 
 said first and second output buffer circuits have respective sense amplifier circuits and output selection circuits,    said sense amplifier circuits in said first and the second output buffer circuits respectively amplify data which are transmitted through said first and second read bit lines, and output the amplified data,    said output selection circuits in said first and second output buffer circuits respectively output data from said sense amplifier circuits in said first and second output buffer circuits to said first and second output ports in said read mode, and respectively output data transmitted through said first and second bypass lines to the first and second output ports in said bypass mode, and    in the layout structure in plan view,    said first memory cell array, said sense amplifier circuit in said first output buffer circuit and said output selection circuit in said first output buffer circuit are arranged in this order in a row, and    said second memory cell array, said sense amplifier circuit in said second output buffer circuit and said output selection circuit in said second output buffer circuit are arranged in this order in a row.    
   
   
       7 . The semiconductor device according to  claim 3 , wherein 
 said output buffer circuit has:    a sense amplifier circuit which amplifies data transmitted through said read bit line, and outputs the amplified data; and    an output selection circuit which outputs data from said sense amplifier circuit to said output port in said read mode, and outputs data transmitted through said bypass line to said output port in said bypass mode, and    in the layout structure in plan view,    said memory cell array, said sense amplifier circuit and said output selection circuit are arranged in this order in a row.    
   
   
       8 . A semiconductor device comprising a semiconductor memory section that has a write mode, a read mode and a bypass mode, wherein 
 said semiconductor memory section includes:    a memory cell array having a plurality of memory cells arranged in a predetermined direction;    an input port into which data is inputted;    an output port from which data is outputted;    a plurality of read word lines respectively connected to said plurality of memory cells in said memory cell array;    a plurality of write word lines respectively connected to said plurality of memory cells in said memory cell array;    a decoder circuit which activates any one of said plurality of write word lines in said write mode, and activates any one of said plurality of read word lines in said read mode;    an input buffer circuit which receives data having been inputted into said input port, and outputs the received data;    a write bit line which extends from said input buffer circuit to said memory cell array, and transmits data outputted from said input buffer circuit to said memory cell array;    an output buffer circuit which outputs received data to said output port; and    a read bit line which extends from said memory cell array to said output buffer circuit, and transmits data from said memory cell array to said output buffer circuit,    said write bit line is extended from said memory cell array to said output buffer circuit, and    said output buffer circuit outputs data transmitted through said read bit line to said output port in said read mode, and outputs data transmitted through said write bit line to said output port in said bypass mode.    
   
   
       9 . The semiconductor device according to  claim 8 , wherein 
 said input buffer circuit has:    a data switch circuit which outputs data, having been inputted into said input port, based upon a control signal in said write mode, and outputs data, having been inputted into said input port, regardless of said control signal in said bypass mode; and    a bit line driver circuit which receives data outputted from said data switch circuit, and outputs the received data to said write bit line, and    said output buffer circuit has:    a sense amplifier circuit which amplifies data transmitted through said read bit line, and outputs the amplified data; and    an output selection circuit which outputs data from said sense amplifier circuit to said output port in said read mode, and outputs data transmitted through said write bit line to said output port in said bypass mode    
   
   
       10 . The semiconductor device according to  claim 8 , wherein 
 in the layout structure in plan view, said memory cell array is arranged between said input buffer circuit and said output buffer circuit.    
   
   
       11 . The semiconductor device according to  claim 8 , wherein 
 said memory cell array has a first memory cell column composed of said plurality of memory cells arranged in said predetermined direction, and a second memory cell column composed of a plurality of memory cells arranged in said predetermined direction,    said plurality of read word lines are respectively connected to said plurality of memory cells in said first and second memory cell columns,    said plurality of write word lines are respectively connected to said plurality of memory cells in said first and second memory cell columns,    said write bit line includes: a first write bit line which extends from said input buffer circuit to said first memory cell column and transmits data outputted from said input buffer circuit to said first memory cell column; and a second write bit line which extends from said input buffer circuit to said second memory cell column and transmits data outputted from said input buffer circuit to said second memory cell column,    said read bit line includes a first read bit line which extends from said first memory cell column to said output buffer circuit and transmits data outputted from said first memory cell column to said output buffer circuit, and a second read bit line which extends from said second memory cell column to said output buffer circuit and transmits data outputted from said second memory cell column to said output buffer circuit,    said first write bit line is extended from said first memory cell column to said output buffer circuit,    said input buffer circuit outputs data, having been inputted into said input port, to either the first or second write bit line based upon a first selection signal in said write mode, and outputs the data not to said second write bit line but to said first write bit line in said bypass mode, and    said output buffer circuit outputs either data transmitted through said first or second read bit line to said output port based upon the second selection signal in said read mode, and outputs data transmitted through said first write bit line to said output port in said bypass mode.    
   
   
       12 . A semiconductor device comprising a semiconductor memory section that has a write mode, a read mode and a bypass mode, wherein 
 said semiconductor memory section includes:    a memory cell array having a plurality of memory cells arranged in a predetermined direction;    an input port into which data is inputted;    an output port from which data is outputted;    a plurality of read word lines respectively connected to said plurality of memory cells in the memory cell array;    a plurality of write word lines respectively connected to said plurality of memory cells in said memory cell array;    a decoder circuit which activates any one of said plurality of write word lines in said write mode, and activates any one of said plurality of read word lines in said read mode;    an input buffer circuit which receives data having been inputted into said input port, and outputs the received data;    a write bit line which extends from said input buffer circuit to said memory cell array, and transmits data outputted from said input buffer circuit to said memory cell array;    an output buffer circuit which outputs received data to said output port; and    a read bit line which extends from said memory cell array to said output buffer circuit, and transmits data from said memory cell array to said output buffer circuit,    said read bit line is extended from said memory cell array to said input buffer circuit, and    said input buffer circuit outputs data, having been inputted into said input port, not to said read bit line but to said write bit line in said write mode, and outputs data, having been inputted into said input port, to said read bit line in said bypass mode.    
   
   
       13 . The semiconductor device according to  claim 12 , wherein 
 said input buffer circuit has:    a bit line switch circuit which does not output data, having been inputted into said input port, to said read bit line in said read mode and said write mode, and outputs the data to said read bit line in said bypass mode; and    a bit line driver circuit which outputs data, having been inputted into said input port, to said write bit line based upon a control signal in said write mode.