US2007046313A1PendingUtilityA1

Mounting Spring Elements on Semiconductor Devices, and Wafer-Level Testing Methodology

Assignee: FORMFACTOR INCPriority: Nov 16, 1993Filed: Oct 25, 2006Published: Mar 1, 2007
Est. expiryNov 16, 2013(expired)· nominal 20-yr term from priority
H10W 72/543H10W 72/551H10W 72/555H10W 72/534H10W 74/00H10W 90/22H10W 90/20H10W 72/01H10W 90/754H10W 72/856H10W 72/547H10W 72/07554H10W 72/5524H10W 72/5522H10W 72/952H10W 72/951H10W 72/923H10W 72/29H10W 72/59H10W 72/019H10W 70/05H10W 46/501H10W 90/00H10W 72/0198H10W 72/20H10W 72/00H10W 72/07533H10W 72/07532H10W 72/074H10W 72/07236H10W 72/354H10W 72/352H10W 72/325H10W 72/01331H10W 90/722H10W 72/255H10W 72/223H10W 72/252H10W 72/242H10W 72/01251H10W 72/01255H10W 72/01225H10W 72/01223H10W 72/01204H10P 74/23H10P 72/74H10W 72/5525H10W 72/523H10W 46/00H10W 90/701H10W 74/15H10W 74/012H10W 72/075H10W 70/093Y10T29/4922G01R 1/07342Y10T29/49144C23C 18/165H05K 3/20H05K 3/3421C25D 21/02H05K 2201/1031H05K 2201/10757Y10T29/49171Y10T29/49117B23K 1/0008Y10T29/49208H05K 2201/068H05K 2201/10318Y10T428/12528Y10T29/49147G01R 31/2863H05K 3/308Y10T29/49169B23K 20/004H01R 12/52H05K 2201/10909Y10T29/49004H05K 3/326H05K 1/141G01R 31/2884Y10T29/4913Y10S977/723H05K 2201/10378G01R 31/2886H05K 2201/10734Y10T29/49204Y10T29/49149H05K 3/368H05K 3/4092Y10T428/12396H05K 7/1069H05K 2201/0397H05K 3/3426H05K 2201/10878C23C 18/1605H05K 2201/10719Y10T29/49812Y10S977/712B23K 2101/40H05K 3/4015H05K 2201/10946G01R 31/2856C25D 7/123C25D 5/605C25D 5/22Y02P70/50
52
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same resilient contact structures can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements of the present invention as the resilient contact structures, burn-in can be performed at temperatures of at least 150° C., and can be completed in less than 60 minutes.

Claims

exact text as granted — not AI-modified
1 - 46 . (canceled)  
     
     
         47 . An apparatus comprising: 
 a semiconductor wafer comprising a plurality of unsingulated semiconductor devices on said wafer, said semiconductor devices comprising a plurality of resilient contact structures mounted thereon;    a test board comprising a plurality of contact elements, said test board disposed in proximity to said semiconductor wafer, forming pressure connections between ones of said resilient contact structures and corresponding contact elements of said test board; and    means for exercising at least one of said semiconductor devices.    
     
     
         48 . The apparatus of  claim 47  further comprising means for elevating a temperature of said at least one semiconductor device while exercising said at least one semiconductor device.  
     
     
         49 . The apparatus of  claim 48 , wherein said means for elevating is capable of elevating said temperature of said at least one semiconductor devices to least 125° C.  
     
     
         50 . The apparatus of  claim 47 , wherein said means for exercising exercises said at least one semiconductor device by providing electrical signals through said contact elements of said test board to said ones of said resilient contact structures.  
     
     
         51 . The apparatus of  claim 50  further comprising means for monitoring a response of said at least one semiconductor device to said electrical signals.  
     
     
         52 . The apparatus of  claim 51  further comprising means for evaluating said response.

Join the waitlist — get patent alerts

Track US2007046313A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.