Structure of an ultra-thin wafer level stack package

Abstract

A structure of an ultra-thin wafer level stack package is provided. A method for manufacturing the structure includes providing a first wafer having a plurality of base chips thereon, selectively binding the first wafer to a second substrate, lapping the first wafer to reduce its thickness, dicing the lapped first wafer, bonding a plurality stack chips to each base chip and packaging the base chip with the bonded stack chips to form an IC package. Thus, each IC package comprises at least a base chip and a stack chip. The IC package has a size almost identical to the base chip and a thickness a little larger than the combined thickness of the base chip and the stack chip. If a known good die inspection of the base chips and stack chips are carried out prior to wafer level packaging, overall yield of the IC package is increased.

1 . A structure of a stack package, comprising: 
 an independent chip set, obtained by dicing an selectively adhered wafer, wherein the selectively adhered wafer comprises: 
 a first wafer and a second substrate bonded to the first wafer through a plurality of adhesives, wherein the first wafer has a plurality of base chips thereon, a distance between the first wafer and the second substrate is equal to a thickness of the adhesive; and  
 wherein each independent chip set comprises a base chip and a portion of the second substrate.  
   
     
     
         2 . The structure of  claim 1 , wherein the independent chip set is obtained by cutting a second surface of the first wafer of the selectively adhered wafer, wherein a depth of cutting is greater than a thickness of the first wafer but smaller than the total thickness of the first wafer and the adhesive; and 
 cutting a second surface of the second substrate of the selectively adhered wafer, wherein a depth of cutting is greater than a thickness of the second substrate but smaller than the total thickness of the second substrate and the adhesive.    
     
     
         3 . The structure of  claim 1 , further comprises a stack chip bonded to the base chip of the independent chip set.  
     
     
         4 . The structure of  claim 1 , further comprises a plurality of stack chips bonded to the base chip of the independent chip set.  
     
     
         5 . The structure of  claim 1 , wherein the first wafer has a thickness between about 30 μm to 250 μm.  
     
     
         6 . The structure of  claim 1 , wherein the first wafer has a thickness between about 30 μm to 80 μm.  
     
     
         7 . The structure of  claim 1 , wherein the second substrate comprises a plurality of chips, and a position of each of the chips is matched with the first wafer.  
     
     
         8 . The structure of  claim 1 , wherein the second substrate comprises a glass substrate.  
     
     
         9 . The structure of  claim 1 , wherein the second substrate comprises a silicon wafer substrate.  
     
     
         10 . The structure of  claim 1 , wherein the second substrate comprises a plastic substrate.  
     
     
         11 . The structure of  claim 1 , wherein the second substrate comprises an acrylic substrate.  
     
     
         12 . The structure of  claim 1 , wherein the second substrate comprises a polymer substrate.  
     
     
         13 . The structure of  claim 1 , wherein the second substrate is fabricated using a transparent material.  
     
     
         14 . The structure of  claim 1 , wherein the second substrate is fabricated using a non-transparent material.