US2007045700A1PendingUtilityA1
Semiconductor apparatus and manufacturing method thereof
Est. expiryAug 26, 2025(expired)· nominal 20-yr term from priority
H10D 62/127H10D 62/393H10D 30/668
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Claims
Abstract
A semiconductor apparatus according to the present invention includes a P type base diffusion layer on an N type epitaxial layer, a plurality of gate electrodes reaching to the N− epitaxial layer, an N type source diffusion layer in a region near the gate electrodes, a first P+ type diffusion layer in a region where the N type source diffusion layer is not formed, and a second P+ type diffusion layer formed separated from the first P+ type diffusion layer, deeper than the first P+ type diffusion layer, and shallower than a bottom of a trench.
Claims
exact text as granted — not AI-modified1 . A semiconductor apparatus comprising:
a first semiconductor layer of a first conductive type; a low concentration base region of a second conductive type formed on the first semiconductor layer; a gate electrode formed in a trench with insulating film on an inner surface of the trench that is formed to reach the first semiconductor layer from a surface of the low concentration base region; a source region of the first conductive type formed, contacting the insulating film, on the surface of the low concentration base region; a first high concentration base region of the second conductive type formed on the surface of the low concentration base region; and a second high concentration base region of the second conductive type formed to be included inside the low concentration base region, separated from the first high concentration base region, and closer to the first high concentration base region than a depth order of a bottom surface of the trench.
2 . The semiconductor apparatus according to claim 1 , wherein the high concentration base region is formed to be contacting a junction between the low concentration base region and the first semiconductor layer.
3 . The semiconductor apparatus according to claim 1 , wherein the second high concentration base region is formed separated from a junction between the low concentration base region and the first semiconductor layer.
4 . The semiconductor apparatus according to claim 1 , wherein a width of the first high concentration base region is practically the same as a width of the second high concentration base region, and a part of the second high concentration base region is formed straight below the first high concentration base region.
5 . The semiconductor apparatus according to claim 2 , wherein a width of the first high concentration base region is practically the same as a width of the second high concentration base region, and a part of the second high concentration base region is formed straight below the first high concentration base region.
6 . The semiconductor apparatus according to claim 3 , wherein a width of the first high concentration base region is practically the same as a width of the second high concentration base region, and a part of the second high concentration base region is formed straight below the first high concentration base region.
7 . The semiconductor apparatus according to any of claim 1 , wherein the width of the first high concentration base region is different from the width of the second high concentration base region, and a part of the second high concentration base region is formed straight below the first high concentration base region.
8 . The semiconductor apparatus according to any of claim 2 , wherein the width of the first high concentration base region is different from the width of the second high concentration base region, and a part of the second high concentration base region is formed straight below the first high concentration base region.
9 . The semiconductor apparatus according to any of claim 3 , wherein the width of the first high concentration base region is different from the width of the second high concentration base region, and a part of the second high concentration base region is formed straight below the first high concentration base region.
10 . The semiconductor apparatus according to claim 1 , further comprising a third high concentration base region of a second conductive type formed between the first and the second high concentration base regions.
11 . The semiconductor apparatus according to claim 1 , wherein the first semiconductor layer comprises:
a semiconductor substrate of the first conductive type; and an epitaxial layer of the first conductive type formed on the semiconductor substrate, wherein the trench is formed to reach the epitaxial layer.
12 . A method of manufacturing a semiconductor apparatus comprising:
forming a trench on a surface of a first semiconductor layer of a first conductive type; forming a gate electrode in the trench with an insulating film on an inner surface of the trench; forming a low concentration base region of a second conductive type on the surface of the first semiconductor layer; forming a source region of the first conductive type on a surface of the low concentration base region; forming a first high concentration base region of the second conductive type on the surface of the low concentration base region; and forming a second high concentration base region of the second conductive type to be included in the low concentration base region, separated from the first high concentration base region, and closer to the first high concentration base region than a depth order of a bottom surface of the trench.
13 . The method of manufacturing the semiconductor apparatus according to claim 9 , wherein the second high concentration base region is formed by implanting ion to the low concentration base region with higher energy than an energy for the first high concentration base region.Join the waitlist — get patent alerts
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