Single stage implementation of min*, max*, min and/or max to perform state metric calculation in SISO decoder

Abstract

Single stage implementation of min*, max*, min and/or max to perform state metric calculation in soft-in soft-out (SISO) decoder. This allows for calculation of state metrics in an extremely efficient, fast manner. When performing min or max calculations, comparisons are made using 2 element combinations of the available inputs. Subsequently, logic circuitry employs the results of the 2 element comparisons the smallest (min) or largest (max) input. The max or min implementations may be employed as part of the max* and/or min* implementations. For max* and/or min* implementations, simultaneous calculation of appropriate values is performed while determining which input is the smallest or largest. Thereafter, the determination of which input is the smallest or largest is used to select the appropriate resultant value (of the values calculated) for max* and/or min*. Various degrees of precision are employed for the log correction values within the max* and/or min* implementations.

1 . An apparatus that is operable to generate a min* (min-star) result or max* (max-star) result for use in decoding an LDPC (Low Density Parity Check) coded signal, the apparatus comprising: 
 a min block or a max block that is operable to: 
 calculate a min result or a max result from a plurality of inputs; and  
 determine a min value or a max value from among 2 inputs of the plurality of inputs;  
   an intermediate log correction value calculation block that is operable to: 
 calculate a plurality of 2 element log correction values such that each 2 element log correction value corresponds to 2 inputs of the plurality of inputs; and  
 select one 2 element log correction value from the plurality of 2 element log correction values using the determined min value or max value from among 2 inputs of the plurality of inputs; and  
   a final log correction calculation block that is operable to calculate a final log correction value that that corresponds to all inputs of the plurality of inputs; and wherein:    the min result or the max result, the selected one 2 element log correction value, and the final log correction value are individual components of the min* result or the max* result; and    the min* result or the max* result is employed in decoding the LDPC coded signal.    
   
   
       2 . The apparatus of  claim 1 , wherein: 
 an adder that is operable to add the min result or the max result, the selected one 2 element log correction value, and the final log correction value.    
   
   
       3 . The apparatus of  claim 1 , wherein: 
 the min block or a max block is operable calculate a plurality of sign bits that corresponds to differences between selected 2 input pairs of the plurality of inputs; and    the final log correction calculation block employs the plurality of sign bits and the plurality of 2 element log correction values to calculate the final log correction value.    
   
   
       4 . The apparatus of  claim 1 , wherein: 
 the intermediate log correction value calculation block includes a plurality of subtractors that is operable to calculate differences between selected 2 input pairs of the plurality of inputs; and    the intermediate log correction value calculation block is operable to employ the differences to calculate the plurality of 2 element log correction values.    
   
   
       5 . The apparatus of  claim 1 , wherein: 
 the final log correction calculation block is operable to calculate a plurality of possible final log correction values; and    the final log correction calculation block is operable to select the final log correction value from the plurality of possible final log correction values.    
   
   
       6 . The apparatus of  claim 1 , wherein: 
 the final log correction calculation block is operable to calculate differences between selected pairs of 2 element log correction values within the plurality of 2 element log correction values;    the final log correction calculation block is operable to employ the differences to calculate a plurality of possible final log correction values; and    the final log correction calculation block is operable to select the final log correction value from the plurality of possible final log correction values.    
   
   
       7 . The apparatus of  claim 1 , further comprising: 
 at least one multiplexor (MUX); and wherein:    the final log correction calculation block is operable to calculate differences between selected pairs of 2 element log correction values within the plurality of 2 element log correction values;    the final log correction calculation block is operable to employ the differences to calculate a plurality of possible final log correction values;    the plurality of possible final log correction values is provided to the at least one MUX; and    a select signal, that is provided to the at least one MUX, is one of the differences between one pair of 2 element log correction values within the plurality of 2 element log correction values.    
   
   
       8 . The apparatus of  claim 1 , wherein: 
 the final log correction calculation block is operable to determine differences between selected pairs of 2 element log correction values within the plurality of 2 element log correction values; and    each difference between the selected pairs of 2 element log correction values is one predetermined value selected from a plurality of predetermined values.    
   
   
       9 . The apparatus of  claim 1 , wherein: 
 the intermediate log correction value calculation block is operable to determine the plurality of 2 element log correction values such that each 2 element log correction value corresponds to 2 inputs of the plurality of inputs;    a first 2 element log correction value of the plurality of 2 element log correction values is a first predetermined number selected from a plurality of predetermined values; and    a second 2 element log correction value of the plurality of 2 element log correction values is a second predetermined number selected from the plurality of predetermined values.    
   
   
       10 . The apparatus of  claim 1 , wherein: 
 the apparatus is a communication device that is implemented within at least one of a satellite communication system, a High Definition Television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.    
   
   
       11 . An apparatus that is operable to generate a min* (min-star) result or max* (max-star) result for use in decoding an LDPC (Low Density Parity Check) coded signal, the apparatus comprising: 
 a min block or a max block that is operable to: 
 calculate a min result or a max result from a plurality of inputs; and  
 determine a min value or a max value from among 2 inputs of the plurality of inputs;  
   an intermediate log correction value calculation block that is operable to: 
 calculate a plurality of 2 element log correction values such that each 2 element log correction value corresponds to 2 inputs of the plurality of inputs; and  
 select one 2 element log correction value from the plurality of 2 element log correction values using the determined min value or max value from among 2 inputs of the plurality of inputs;  
   a final log correction calculation block that is operable to calculate a final log correction value that that corresponds to all inputs of the plurality of inputs; and    an adder that is operable to add the min result or the max result, the selected one 2 element log correction value, and the final log correction value thereby generating a min* result or a max* result for use in decoding the LDPC coded signal; and wherein:    the min block or a max block is operable calculate a plurality of sign bits that corresponds to differences between selected 2 input pairs of the plurality of inputs; and    the final log correction calculation block employs the plurality of sign bits and the plurality of 2 element log correction values to calculate the final log correction value.    
   
   
       12 . The apparatus of  claim 11 , wherein: 
 the final log correction calculation block is operable to calculate differences between selected pairs of 2 element log correction values within the plurality of 2 element log correction values;    the final log correction calculation block is operable to employ the differences to calculate a plurality of possible final log correction values; and    the final log correction calculation block is operable to select the final log correction value from the plurality of possible final log correction values.    
   
   
       13 . The apparatus of  claim 11 , wherein: 
 the final log correction calculation block is operable to determine differences between selected pairs of 2 element log correction values within the plurality of 2 element log correction values; and    each difference between the selected pairs of 2 element log correction values is one predetermined value selected from a plurality of predetermined values.    
   
   
       14 . The apparatus of  claim 11 , wherein: 
 the intermediate log correction value calculation block is operable to determine the plurality of 2 element log correction values such that each 2 element log correction value corresponds to 2 inputs of the plurality of inputs;    a first 2 element log correction value of the plurality of 2 element log correction values is a first predetermined number selected from a plurality of predetermined values; and    a second 2 element log correction value of the plurality of 2 element log correction values is a second predetermined number selected from the plurality of predetermined values.    
   
   
       15 . The apparatus of  claim 11 , wherein: 
 the apparatus is a communication device that is implemented within at least one of a satellite communication system, a High Definition Television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.    
   
   
       16 . A method for generating a min* (min-star) result or max* (max-star) result for use in decoding an LDPC (Low Density Parity Check) coded signal, the apparatus comprising: 
 calculating a min result or a max result from a plurality of inputs;    determining a min value or a max value from among 2 inputs of the plurality of inputs;    calculating a plurality of 2 element log correction values such that each 2 element log correction value corresponds to 2 inputs of the plurality of inputs;    selecting one 2 element log correction value from the plurality of 2 element log correction values using the determined min value or max value from among 2 inputs of the plurality of inputs;    calculating a final log correction value that that corresponds to all inputs of the plurality of inputs; and    employing the min result or the max result, the selected one 2 element log correction value, and the final log correction value when decoding the LDPC coded signal.    
   
   
       17 . The method of  claim 16 , further comprising: 
 adding the min result or the max result, the selected one 2 element log correction value, and the final log correction value.    
   
   
       18 . The method of  claim 16 , further comprising: 
 calculating a plurality of sign bits that corresponds to differences between selected 2 input pairs of the plurality of inputs; and    employing the plurality of sign bits and the plurality of 2 element log correction values to calculate the final log correction value.    
   
   
       19 . The method of  claim 16 , further comprising: 
 determining differences between selected pairs of 2 element log correction values within the plurality of 2 element log correction values; and wherein:    each difference between the selected pairs of 2 element log correction values is one predetermined value selected from a plurality of predetermined values.    
   
   
       20 . The method of  claim 16 , wherein: 
 the method is performed in a communication device; and    the communication device is implemented within at least one of a satellite communication system, a High Definition Television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.