Memory control apparatus executing prefetch instruction

Abstract

A memory controller reads data from DRAM at a request from a plurality of masters. It includes a prefetch buffer for storing a result of a pre-reading operation, and a register for setting a specific master among a plurality of masters. When a master requests a read, the memory controller pre-reads data subsequent to the requested data, and determines whether or not the master is a specific master set by the register. If the master is the specific master set by the register, then the result of the pre-read is stored in the prefetch buffer. Thus, the prefetch buffer can effectively function in a system having a plurality of masters.

1 . A memory control apparatus which performs a reading operation on a memory device at a request of a plurality of masters, comprising: 
 read means for pre-reading data subsequent to data which any of the plurality of masters requests to read;    a prefetch buffer for holding a result of the pre-reading;    set means for setting a specific master among the plurality of masters; and    control means for determining whether or not a present master which issues a read request is the specific master set by said set means when the read request is issued from the present master, storing a result of the pre-reading in said prefetch buffer when it is determined that the present master is the specific master, and refraining from changing the content of said prefetch buffer when it is determined that the present master is not the specific master.    
   
   
       2 . The memory control apparatus according to  claim 1 , wherein said set means can arbitrarily set the specific master among the plurality of masters.  
   
   
       3 . The memory control apparatus according to  claim 1 , wherein said apparatus is connected to the plurality of masters through a shared bus.  
   
   
       4 . The memory control apparatus according to  claim 1 , wherein said read means simultaneously pre-reads data and reads data requested by the present master.  
   
   
       5 . The memory control apparatus according to  claim 1 , wherein said read means simultaneously reads data requested by the present master and pre-reads data subsequent to the requested data.  
   
   
       6 . The memory control apparatus according to  claim 5 , wherein said prefetch buffer stores data requested by the master and data subsequent to the requested data.  
   
   
       7 . The memory control apparatus according to  claim 1 , wherein said prefetch buffer stores one or more sets of information including data, an address of the data, and a flag indicating the validity of the data.  
   
   
       8 . (canceled)  
   
   
       9 . The memory control apparatus according to  claim 7 , wherein when the present master requests a write, a requested address is compared with an address of data stored in said prefetch buffer, and the flag is changed into a nullified state when the addresses match each other.  
   
   
       10 . The memory control apparatus according to  claim 7 , wherein when the present master requests a write, a requested address is compared with an address of data stored in said prefetch buffer, and data stored in said prefetch buffer is replaced with data to be written when the addresses match each other.  
   
   
       11 . The memory control apparatus according to  claim 1 , wherein said set means can set a plurality of specific masters.