Clock recovery circuit

Abstract

A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.

1 . A clock recovery circuit in which a timing jitter in a recovered clock is suppressed, the clock recovery circuit comprising: 
 transceiver means for supplying a data signal, which is based on serial data having a regular bit pattern during a first period, and is based on serial data having an arbitrary bit pattern during a second period following the first period;    a duty factor controller for adjusting a data transition characteristic of the transceiver means so as to reduce a duty factor error in a data signal supplied from the transceiver means in the first period, and having the adjusted data transition characteristic stored; and    a clock recovery unit for recovering, from the data signal supplied from the transceiver means, a clock synchronized with the data signal in the second period.    
   
   
       2 . The clock recovery circuit of  claim 1 , wherein the transceiver means includes: 
 a driver for supplying a differential data signal; and    a receiver for receiving the differential data signal from the driver and supplying a single end signal corresponding to the differential data signal,    wherein a data transition characteristic of the driver or the receiver is adjusted by the duty factor controller.    
   
   
       3 . The clock recovery circuit of  claim 1 , wherein the duty factor controller includes an integrator circuit for integrating the data signal so as to output an analog voltage representing a duty factor error in the data signal.  
   
   
       4 . The clock recovery circuit of  claim 3 , wherein the duty factor controller further includes an analog-to-digital converter for giving the transceiver means a digital signal according to the analog output voltage from the integrator circuit as a duty factor control signal.  
   
   
       5 . The clock recovery circuit of  claim 1 , wherein the duty factor controller includes: 
 a delay circuit for generating a delayed data signal that is delayed by one data interval with respect to the data signal; and    a logic circuit for giving the transceiver means a duty factor control signal according to a plurality of logical operation results of the data signal and the delayed data signal.    
   
   
       6 . The clock recovery circuit of  claim 1 , wherein the duty factor controller includes means for detecting a phase error in the clock with respect to the data signal and giving the transceiver means a duty factor control signal according to a magnitude of the phase error.  
   
   
       7 - 12 . (canceled)